Antenna Package Impedance Matching via Dielectric Thickness Variation

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Solution Overview

Problem

The integration of high-performance chips with complex systems faces challenges in manufacturing at a reasonable cost while maintaining quality and reliability, due to impedance mismatch in radio frequency circuits and thermal expansion coefficient differences between heterogeneous materials, leading to signal loss and increased manufacturing complexity.

Innovation Solution

An integrated antenna package structure with a substrate, dielectric layer, molding layer, antenna layer, and protection layer, featuring an impedance matching structure controlled by a control chip, which addresses impedance mismatch and stress issues through tunable matching and stress distribution, using a panel level package process for increased production efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If heterogeneous integration package is used to reduce space and thickness, then miniaturization is achieved, but impedance mismatch causes signal loss and requires extra impedance match process

Engineering Contradiction:
Improvepackage sizeVSAvoidsignal transmission quality
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by creating a non-uniform dielectric layer with varying thickness around the antenna structure. The dielectric layer has different thickness regions (first thickness and second thickness) that locally adjust the electromagnetic field distribution and impedance characteristics at specific locations, thereby achieving impedance matching without adding external components.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes physical parameters by varying the dielectric constant and thickness of the dielectric layer. By controlling the dielectric material properties and geometric dimensions (thickness variations), the impedance characteristics are adjusted to achieve matching between different components in the heterogeneous integration package.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If heterogeneous materials are integrated to achieve diversified solutions, then flexibility is improved, but thermal expansion coefficient difference increases manufacturing difficulty and cost

Engineering Contradiction:
Improvesolution diversityVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent addresses thermal stress by creating local variations in the dielectric layer thickness, which distributes stress more evenly across the heterogeneous material interfaces. This local structural adjustment reduces the overall manufacturing complexity despite using diverse materials.

Inventive Principle:
Principle #3Local quality

3Reliability

If extra impedance match process is added after redistribution integration, then signal loss is reduced, but manufacturing process complexity increases

Engineering Contradiction:
Improvesignal transmission qualityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by pre-configuring the dielectric layer with specific thickness variations during the initial packaging process. This preliminary structural design inherently provides impedance matching functionality, eliminating the need for subsequent separate impedance matching processes and reducing overall manufacturing complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10886593B2Structure of integrated radio frequency multi-chip package and method of fabricating the same
Publication Date: 2021.01.05 IND TECH RES INST
  • US10886593B2 patent drawing
  • US10886593B2 patent drawing
  • US10886593B2 patent drawing

AI summary

An antenna package structure comprises a substrate with a first surface and a second surface; a dielectric layer, disposed on the first surface of the substrate comprises at least a impedance matching structure and an interconnection structure; a molding layer, disposed on the dielectric layer comprises a plurality of chips wherein a control chip electrically connects to the impedance matching structure and a plurality of conducting structures; an antenna layer, disposed on the second surface of the substrate comprising at least an antenna electrically connects to the substrate; and a protection layer covers the antenna layer.