Antenna Package Via Structure for Low-Interference Signal Routing
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Solution Overview
Problem
Existing semiconductor packages face challenges in minimizing mutual interference between components, particularly in mm-wave and 5G antenna modules, while ensuring miniaturization and maintaining electrical reliability and flexibility in mounting positions.
Innovation Solution
The semiconductor package design includes a redistribution substrate with specific via and interconnection patterns, a molding layer covering semiconductor chips, and an antenna substrate with shielding layers, which reduces thickness and minimizes internal connection lines, enhancing electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional antenna module designs are used, then electrical connectivity is achieved, but mutual interference between components occurs and package size cannot be minimized
Solution Approach 1:
The patent divides the antenna module into separate functional layers: an antenna substrate containing antenna patterns, a redistribution substrate for signal routing, and a semiconductor chip for processing. This segmentation isolates the antenna patterns from other components, reducing mutual interference while maintaining electrical connectivity through controlled via structures.
Solution Approach 2:
The patent transitions from planar interconnections to three-dimensional via structures that penetrate through insulating layers. The via portions extend vertically from the antenna substrate through the redistribution substrate, enabling electrical connection in the thickness direction and reducing horizontal interference between components.
2Reliability
If conventional packaging structures are used, then components are protected, but package thickness increases and mounting flexibility is reduced
Solution Approach 1:
The patent embeds the redistribution substrate within the antenna substrate structure, with via portions penetrating through insulating layers to connect different functional elements vertically. This nesting approach consolidates multiple functions into a compact vertical arrangement, reducing overall package thickness while maintaining protection.
3Reliability
If more internal connection lines are added, then electrical connectivity improves, but package complexity and size increase
Solution Approach 1:
The patent resolves complex interconnections by transitioning to vertical via structures that penetrate through insulating layers. Instead of routing multiple horizontal connection lines across the substrate, signals are connected vertically through via portions, simplifying the interconnection architecture while maintaining electrical connectivity.
Data Source
AI summary
A semiconductor package includes a redistribution substrate including a first surface and a second surface that are opposite to each other, an antenna substrate on the first surface and including a first insulating portion and antenna patterns on a top surface of the first insulating portion, and a first semiconductor chip on the second surface. The redistribution substrate includes a second insulating portion, and a redistribution pattern in the second insulating portion. The redistribution pattern includes an interconnection portion extending parallel to a top surface of the second insulating portion, and a via portion protruding from the interconnection portion toward the first surface. A width of the via portion decreases as a height in a direction from the second surface toward the first surface increases. The active surface of the first semiconductor chip is adjacent to the second surface.