Wafer-Level Antenna Packaging With Dielectric Cavity Venting
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Solution Overview
Problem
The demand for smaller and more advanced semiconductor packaging techniques, particularly for high-performance devices with integrated antennas, is not adequately met by existing methods, which struggle to efficiently integrate antenna structures into wafer-level packaging while ensuring reliable signal transmission and mechanical support.
Innovation Solution
The development of a chip packaging process involving a temporary carrier with a redistribution layer, through interlayer vias, and a dielectric structure with a cavity and vent, allowing for the integration of antenna patterns on the dielectric layer, which enhances bandwidth and mechanical support, and includes a molding chase for efficient material injection and removal processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If antenna structures are integrated into wafer-level packaging, then bandwidth and signal transmission performance are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The packaging structure is divided into multiple functional layers including dielectric layers, conductive layers, and molding layers. Each layer serves specific purposes: dielectric layers provide insulation and mechanical support, conductive layers form antenna patterns and interconnections, and molding layers provide protection. This segmentation allows complex antenna functions to be achieved through coordinated simple layers.
Solution Approach 2:
The patent implements a multi-layer nested structure where conductive antenna patterns are embedded within dielectric layers, which are in turn enclosed by molding layers. Through-holes penetrate multiple layers to provide vertical interconnections. This nesting approach integrates antenna, interconnection, and protection functions within a compact wafer-level package.
2Volume of moving object
If smaller package sizes are implemented, then device miniaturization is achieved, but manufacturing precision and integration difficulty increase
Solution Approach 1:
Antenna patterns are formed on conductive layers before the final molding step. Through-holes are created and filled with conductive material in advance to establish interconnections. This preliminary formation of antenna structures and interconnections allows subsequent molding to encapsulate everything without compromising antenna geometry or electrical performance, even in small packages.
Solution Approach 2:
The patent utilizes vertical stacking of multiple thin layers to achieve three-dimensional integration within a small footprint. Antenna patterns, dielectric layers, and interconnection structures are arranged in multiple horizontal planes stacked vertically. This dimensional approach allows complex antenna functions to be packed into minimal planar area while maintaining manufacturing feasibility.
3Reliability
If multiple layers and structures are added for antenna integration, then bandwidth is enhanced, but manufacturing time and process complexity increase
Solution Approach 1:
The patent combines antenna formation, interconnection creation, and package encapsulation into an integrated multi-layer manufacturing process. Conductive layers are deposited and patterned to simultaneously create antenna elements and interconnection traces. Dielectric layers are stacked to provide both insulation and mechanical support. Molding encapsulates all structures in a single operation. This merging of functions into unified process steps enhances bandwidth while maintaining manufacturing efficiency.
Data Source
AI summary
A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.