Antenna Array Receiver Circuit for TI-ADC Spur Suppression
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Solution Overview
Problem
In 5G antenna array systems, time-interleaved analog-to-digital converters (ADCs) face mismatch errors leading to degraded spurious-free dynamic range (SFDR) due to timing skew, phase, gain, and DC offset mismatches, which are not effectively mitigated by existing redundancy methods.
Innovation Solution
Implementing a receiver circuit with multiple time-interleaved ADCs in each receiver, where each receiver uses distinct selection sequences for sub ADC operation, signal chopping, and receive path swapping to decorrelate error signals across the array, thereby suppressing spurious components relative to coherent information-bearing signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time-interleaved ADCs are used to increase conversion rate, then productivity is improved, but measurement precision deteriorates due to mismatch effects
Solution Approach 1:
The system divides the ADC functionality into multiple sub-ADCs operating in parallel with time-interleaved architecture, where each sub-ADC handles a portion of the sampling tasks. This segmentation enables higher overall conversion rates while managing the complexity of individual converter units.
Solution Approach 2:
The invention introduces randomization of sampling parameters including variable sampling rates, adjustable timing offsets, and dynamic phase shifts across different sub-ADCs. By continuously varying these parameters, the system prevents consistent mismatch patterns that cause spurious components, thereby improving SFDR while maintaining high conversion rates.
2Measurement precision
If redundant sub ADCs are added to spread errors, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The system implements a randomization strategy where not all sub-ADCs are actively used at every sampling instant. Instead, subsets of sub-ADCs are selectively activated with randomized timing and phase relationships. This partial utilization approach achieves error spreading and SFDR improvement without requiring all redundant converters to operate simultaneously, thereby reducing effective device complexity.
Solution Approach 2:
The invention introduces dynamic control mechanisms that randomly adjust which sub-ADCs are active, their sampling phases, and their timing offsets. This dynamic reconfiguration prevents static mismatch patterns from causing consistent spurious components, achieving improved measurement precision through temporal variability rather than through static redundancy of all components.
3Loss of energy
If multiple ADCs are integrated into one chip for cost and power efficiency, then loss of energy is reduced, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The system compensates for manufacturing variations by introducing randomizable parameters including variable sampling rates, adjustable timing offsets, and dynamic phase shifts for each sub-ADC. These parameters can be programmed and adjusted to compensate for process variations, allowing integrated ADCs to achieve consistent performance despite manufacturing tolerances.
Solution Approach 2:
The invention implements calibration and adjustment mechanisms that measure the actual performance of each integrated sub-ADC and apply compensating parameter adjustments. Through feedback-based tuning of sampling rates, timing offsets, and phase relationships, the system compensates for manufacturing mismatches and achieves uniform performance across all integrated converters.
Data Source
AI summary
A receiver circuit for an antenna array system (AAS) is disclosed. The receiver circuit (10) comprises a set of receivers (151-15p). Each receiver (151-15p) comprises a first TI-ADC (351) in a receive path of the receiver. The first TI-ADC (351) comprises a plurality of sub ADCs (A1-AM+N). Each receiver (151-15p) comprises a control circuit (40) configured to select which sub ADC (A1-AM+N) is to operate on what input sample based on a first selection sequence. The control circuits (40) in the different receivers (151-15p) in said set of receivers (151-15p) are configured to use different first selection sequences.