Antenna Switch Gate Resistance Optimization for Distortion Reduction

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Solution Overview

Problem

Existing antenna switches for mobile communication devices face challenges in reducing intermodulation distortion for WCDMA systems and harmonic distortion for GSM systems, with current solutions failing to achieve desired levels of distortion reduction and operation reliability over extended periods.

Innovation Solution

The semiconductor IC incorporates high-frequency switches with specific voltage-current characteristics for the gate resistances and additional capacitances, and a DC boost circuit with optimized resistance values to manage RF leak signals and improve distortion suppression.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If conventional antenna switches are used for mobile communication devices, then basic switching function is achieved, but intermodulation distortion for WCDMA systems and harmonic distortion for GSM systems cannot be reduced to desired levels

Engineering Contradiction:
Improveintermodulation distortion and harmonic distortionVSAvoidoperation reliability
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent applies local quality by assigning different resistance values to different gate resistances (Rg1, Rg2, Rg3, Rg4) based on their position in the circuit. Specifically, Rg1 and Rg4 have different resistance values than Rg2 and Rg3, optimizing the suppression of RF leak signals at different locations to reduce intermodulation and harmonic distortion while maintaining switching reliability.

Inventive Principle:
Principle #3Local quality

2Object-affected harmful factors

If gate resistances are optimized to reduce distortion, then intermodulation distortion and harmonic distortion are reduced, but operation reliability over extended periods deteriorates

Engineering Contradiction:
ImprovedistortionVSAvoidlifespan
Core Design Contradiction:
Object-affected harmful factorsVSDuration of action of stationary object

Solution Approach 1:

The patent employs parameter changes by carefully selecting specific resistance values for the gate resistances (Rg1-Rg4) to optimize the balance between distortion reduction and operational reliability. The resistance values are chosen to suppress RF leak signals effectively while avoiding excessive current or voltage stress that would reduce the lifespan of the switch circuit.

Inventive Principle:
Principle #35Parameter changes

3Object-affected harmful factors

If RF leak signals are suppressed to reduce distortion, then intermodulation distortion and harmonic distortion are reduced, but voltage fluctuations increase affecting switch stability

Engineering Contradiction:
ImproveRF leak signalsVSAvoidvoltage stability
Core Design Contradiction:
Object-affected harmful factorsVSStability of the object's composition

Solution Approach 1:

The patent uses gate resistances (Rg1, Rg2, Rg3, Rg4) as intermediary elements between the control signal source and the FET gates. These resistances serve dual functions: suppressing RF leak signals that cause distortion while also stabilizing voltage fluctuations by acting as damping elements in the gate circuit.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8676132B2Semiconductor integrated circuit, RF module using the same, and radio communication terminal device using the same
Publication Date: 2014.03.18 RENESAS ELECTRONICS CORP
  • US8676132B2 patent drawing
  • US8676132B2 patent drawing
  • US8676132B2 patent drawing

AI summary

One high-frequency switch Qm supplied with transmit and receive signals to ON, and another high-frequency switch Qn supplied with a signal of another system to OFF are controlled. In the other high-frequency switch Qn, to set V-I characteristics of near-I/O gate resistances Rg1n-Rg3n of a near-I/O FET Qn1 near to a common input/output terminal I/O connected with an antenna are set to be higher in linearity than V-I characteristics of middle-portion gate resistances Rg3n and Rg4n of middle-portion FETs Qn3 and Qn4. Thus, even in case that an uneven RF leak signal is supplied to near-I/O gate resistances Rg1n-Rg3n, and middle-portion gate resistances Rg3n and Rg4n, the distortion of current flowing through the near-I/O gate resistances Rg1n-Rg3n near to the input/output terminal I/O can be reduced.