Antenna Switch Isolation Layout for Lower Substrate Noise Coupling
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Solution Overview
Problem
In semiconductor devices, antenna switches face challenges with high insertion loss due to substrate noise coupling, which complicates design and manufacturing, especially in low noise circuits and system-on-chip designs.
Innovation Solution
The implementation of isolation features adjacent to metal-oxide-semiconductor (MOS) devices on a substrate, including non-implanted semiconductor structures, dummy gates, and resistors, along with a resist protect oxide layer and shallow trench isolations, helps reduce insertion loss without altering the circuit design. This involves configuring resistors and MOS devices with specific spacings and resistivity to minimize parasitic capacitance and substrate noise coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If substrate noise coupling is present in antenna switches, then signal transmission can occur, but insertion loss increases
Solution Approach 1:
The patent extracts and removes the harmful substrate noise coupling effect by introducing isolation structures (such as trenches or insulating layers) between the antenna switch and the substrate. This separation eliminates the harmful electromagnetic coupling while preserving the useful signal transmission path, directly addressing the contradiction between enabling signal transmission and avoiding substrate noise interference.
Solution Approach 2:
The patent introduces intermediary isolation structures (trenches filled with dielectric material, insulating layers, or ground shields) between the antenna switch and the substrate. These intermediaries act as barriers that block substrate noise coupling while allowing the antenna switch to function normally, thereby reducing insertion loss without eliminating signal transmission capability.
2Loss of energy
If isolation structures are added to reduce substrate noise coupling, then insertion loss decreases, but device complexity increases
Solution Approach 1:
The patent applies isolation structures only in specific local regions where substrate noise coupling is most problematic, rather than isolating the entire antenna switch. For example, isolation trenches are placed only adjacent to the active regions or under specific noise-prone areas. This localized approach reduces insertion loss in critical areas while minimizing the overall increase in device complexity and manufacturing steps.
Solution Approach 2:
The patent optimizes parameters of isolation structures (such as trench depth, insulating layer thickness, or ground shield dimensions) to achieve effective noise coupling reduction with minimal added complexity. By carefully tuning these parameters, the design achieves sufficient isolation performance without requiring overly complex or resource-intensive isolation structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces insertion loss and improves antenna switch performance by minimizing substrate noise coupling, achieving better IL performance without additional cost or complexity, applicable to various semiconductor technologies including FinFET for 28 GHz 5G cellular networks.
Implementation Method 1
configuring resistors and MOS devices with specific spacings and resistivity to minimize parasitic capacitance and substrate noise coupling
Data Source
AI summary
A semiconductor device includes a substrate, a first metal-oxide-semiconductor device and a at least one first resistor. The substrate includes a non-doped region. The first metal-oxide-semiconductor device extends into the substrate. The first metal-oxide-semiconductor device is adjacent to the non-doped region. The at least one first resistor is disposed right above the non-doped region and arranged in a first row aligned with the first metal-oxide-semiconductor device in a first direction.


