High-Frequency Antenna Switch Gate Drive for Rise/Fall Time Control
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Solution Overview
Problem
High frequency switch circuits in mobile devices face challenges with significant power loss due to parasitic capacitance in MOSFETs on silicon substrates, and the increase in ports and data bits requires precise control of rise and fall times for high frequency signals, which is difficult to achieve with existing solutions.
Innovation Solution
A semiconductor integrated circuit with a drive circuit and output circuit configuration that includes MOSFETs and a feedback capacitor to control the rise and fall times of output signals, ensuring they remain within a predetermined range across various load capacitances, using specific gate width ratios and feedback capacitance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If MOSFET is used on silicon substrate to replace HEMT, then cost and size are reduced, but parasitic capacitance increases causing significant power loss
Solution Approach 1:
The patent changes the substrate material parameter from typical silicon to high-resistivity silicon, and adjusts MOSFET structure parameters (gate length, gate width, doping concentrations) to reduce parasitic capacitance while maintaining the cost and size advantages of silicon-based MOSFETs over HEMT
2Adaptability or versatility
If the number of ports is increased to support multiple modes and bands, then functionality is improved, but the number of data bits and control complexity increases
Solution Approach 1:
The patent employs dynamic control of rise time and fall time parameters that adapt to different operating conditions and port configurations, allowing the switch circuit to handle multiple modes and bands with optimized performance without linearly increasing control complexity
3Speed
If output resistance is decreased to reduce rise and fall times, then signal transition speed is improved, but high frequency noise components are generated when load capacitance is small
Solution Approach 1:
The patent optimizes the output resistance parameter to a specific range that balances rise/fall time performance with noise suppression, and coordinates this with gate width ratios and feedback capacitance values to achieve acceptable transition speeds without excessive high frequency noise generation
4Speed
If rise time and fall time are set too short, then signal transition speed is improved, but high frequency noise is generated
Solution Approach 1:
The patent establishes optimal ranges for rise time and fall time parameters based on coordinated adjustments of output resistance, gate width ratios, and feedback capacitance, preventing excessively short transition times that would generate high frequency noise while maintaining adequate signal transition speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively sets and maintains consistent rise and fall times for a wide range of load capacitances, reducing power loss and minimizing high frequency noise, thereby enhancing the performance of high frequency switch circuits in mobile devices.
Implementation Method 1
an output circuit including a third MOSFET of the second conductivity type, having a gate connected to the drains of the first and second MOSFETs; and a capacitor connected between the gate of the third MOSFET and a drain of the third MOSFET
Data Source
AI summary
An integrated circuit includes a drive circuit with a first inverter circuit with a first transistor of a first conductivity type and a second transistor of a second conductivity type. The drains of the first and second transistors are connected. An output circuit is provided having a third transistor of the second conductivity with a gate connected to the drains of the first and second transistors. A capacitor is connected between the gate and a drain of the third transistor and has a capacitance greater than 0.5 pF and less than or equal to 3.0 pF. A gate width of the first transistor when divided by a gate width of the third transistor has a value of less than 1/100. The output circuit is configured to output a transmission signal from the drain of the third transistor.