Antenna Switch Substrate Layout for Lower 28 GHz Insertion Loss

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Solution Overview

Problem

Existing antenna switches for 5G wireless communication systems at 28 GHz frequency suffer from high insertion loss (IL) issues, which are not adequately addressed by current CMOS technology improvements.

Innovation Solution

The solution involves replacing doped wells with non-doped silicon regions, using point-shape contact pads, and minimizing the number and length of transistors, as well as adding additional metal layers in the chip and packaging regions to reduce parasitic losses and RF leakage, thereby improving IL performance without altering the circuit design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If existing techniques for improving IL performance are applied (changing silicon substrate to high-resistivity or deepening trench isolation), then insertion loss performance is improved, but these techniques are not available for CMOS technology with 28 GHz operation frequency

Engineering Contradiction:
Improveinsertion lossVSAvoidcompatibility with CMOS technology at 28 GHz
Core Design Contradiction:
Loss of energyVSAdaptability or versatility

Solution Approach 1:

The patent applies local quality by selectively removing doped wells only in specific regions adjacent to MOS devices where RF leakage occurs, rather than changing the entire substrate. This localized modification reduces parasitic losses and improves IL performance while maintaining CMOS technology compatibility at 28 GHz operation frequency.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the electrical parameters of the substrate by removing doped wells and replacing them with intrinsic or lightly-doped regions. This parameter change reduces substrate conductivity in critical areas, thereby reducing RF leakage and improving insertion loss performance without requiring a complete substrate replacement.

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If doped wells are removed and replaced with non-doped silicon regions, then parasitic losses and RF leakage are reduced improving IL performance, but device structure is modified

Engineering Contradiction:
Improveparasitic losses and RF leakageVSAvoiddevice structure
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent extracts the harmful doped well regions from the device structure and replaces them with intrinsic or lightly-doped silicon regions. This extraction removes the source of parasitic losses and RF leakage, improving IL performance while maintaining a relatively simple device structure that is compatible with existing CMOS fabrication processes.

Inventive Principle:
Principle #2Taking out (Extraction)

3Loss of energy

If point-shape contact pads are used instead of conventional contact pads, then RF leakage is reduced improving IL performance, but manufacturing precision requirements increase

Engineering Contradiction:
ImproveRF leakageVSAvoidcontact pad fabrication
Core Design Contradiction:
Loss of energyVSManufacturing precision

Solution Approach 1:

The patent employs asymmetric point-shape contact pads instead of conventional symmetric pad structures. This asymmetric design minimizes the contact area with the substrate, reducing RF leakage paths. The point-shape geometry is specifically designed to achieve optimal RF performance while remaining manufacturable with standard fabrication tolerances.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS12142585B2Devices and methods for enhancing insertion loss performance of an antenna switch
Publication Date: 2024.11.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12142585B2 patent drawing
  • US12142585B2 patent drawing
  • US12142585B2 patent drawing

AI summary

Devices and methods for enhancing insertion loss performance of an antenna switch are disclosed. In one example, a semiconductor device formed to serve as an antenna switch is disclosed. The semiconductor device includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: an intrinsic substrate; a metal-oxide-semiconductor device extending into the intrinsic substrate; and at least one isolation feature extending into and in contact with the intrinsic substrate. The at least one isolation feature is disposed adjacent to the metal-oxide-semiconductor device.