Anti-Back-Sputtering Layer for Defect-Free Conductive Features

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Solution Overview

Problem

Challenges arise during the scaling-down process of semiconductor structures, leading to issues with quality, yield, performance, and reliability, particularly due to defects from back sputtering of underlying conductive layers during hard mask layer patterning.

Innovation Solution

Incorporation of an anti-back sputtering layer with etching selectivity to the hard mask structure, which prevents defects by protecting underlying conductive features during patterning processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the dimensions of semiconductor structures are scaled down to meet increasing computing demand, then computing ability is improved, but quality and yield deteriorate due to defects from back sputtering during patterning

Engineering Contradiction:
Improvecomputing abilityVSAvoidyield
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

An anti-back-sputtering layer is introduced as an intermediary protective layer between the conductive layer and the etching environment during patterning. This layer prevents direct exposure of the conductive layer to back sputtering, thereby eliminating defects while allowing the scaling-down process to continue for improved computing ability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The anti-back-sputtering layer is formed in advance before the patterning process. This preliminary protective layer is deposited on the conductive layer prior to any etching operations, proactively preventing back sputtering defects before they can occur during subsequent manufacturing steps

Inventive Principle:
Principle #10Preliminary action

2Speed

If the dimensions of semiconductor structures are scaled down, then computing ability is improved, but manufacturing precision deteriorates due to defects in conductive features

Engineering Contradiction:
Improvecomputing abilityVSAvoidconductive feature quality
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The anti-back-sputtering layer serves as a protective intermediary that prevents etching damage to the conductive layer during patterning. This ensures that conductive features maintain their intended dimensions and quality even as overall structure sizes are reduced for higher computing performance

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If an anti-back sputtering layer is added to prevent back sputtering defects, then yield is improved, but device complexity increases

Engineering Contradiction:
ImproveyieldVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The anti-back-sputtering layer is designed as a temporary, disposable protective layer that performs its function during the patterning process and is subsequently removed. This disposable approach provides the necessary protection against back sputtering without permanently increasing device complexity, as the layer is discarded after serving its protective purpose

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves the yield of semiconductor fabrication by preventing defects in conductive features, enhancing the reliability and performance of semiconductor structures.

Implementation Method 1

defects (such as short of conductive features) originating from the back sputtering of underlying conductive layer during the patterning of the hard mask layers

Methodology Applied
Scientific EffectBack sputtering: Sputtering

Data Source

PatentUS12476116B2Semiconductor structure with anti-back-sputter layer
Publication Date: 2025.11.18 NAN YA TECH
  • US12476116B2 patent drawing
  • US12476116B2 patent drawing
  • US12476116B2 patent drawing

AI summary

The present application discloses a semiconductor structure and a method for fabricating the semiconductor device. The semiconductor structure includes a substrate; a conductive feature positioned on the substrate; an anti-back sputtering layer positioned on the conductive feature; and a first hard mask structure positioned on the anti-back sputtering layer. The anti-back sputtering layer has etching selectivity to the first hard mask structure.