Anti-dishing Dummy Hardmask for Memory Gate Planarity
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Solution Overview
Problem
In integrated circuit manufacturing, the 'dishing' effect during chemical mechanical polishing (CMP) can lead to shortened gate electrodes at the edges of memory arrays, causing threshold voltage variations and nickel contamination, which can result in partial or complete failure of memory devices.
Innovation Solution
The implementation of a dummy hardmask and/or dummy select gate electrode structure on the isolation structure provides additional rigidity, ensuring planarized and equal height top surfaces for gate electrodes, thereby mitigating the 'dishing' effect and reducing threshold voltage variations and nickel contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) is performed to planarize the surface, then surface flatness is improved, but dishing effect occurs at the edges causing gate electrode shortening
Solution Approach 1:
The patent applies preliminary anti-action by forming dummy hardmask and dummy select gate electrode structures on the isolation structure before CMP processing. These dummy structures pre-compensate for the dishing effect that will occur during CMP, providing additional rigidity to prevent edge erosion and maintain uniform gate electrode lengths across the wafer surface.
Solution Approach 2:
The dummy hardmask and dummy select gate electrode structures serve as intermediary elements between the CMP process and the actual gate electrodes. These intermediary structures absorb the mechanical stress and polishing pressure during CMP, protecting the real gate electrodes from dishing-induced shortening while maintaining surface planarity.
2Manufacturing precision
If CMP processing is applied to achieve planarization, then surface uniformity is improved, but threshold voltage variations increase due to gate electrode shortening
Solution Approach 1:
The dummy structures are formed in advance to counteract the threshold voltage variations that would result from CMP-induced gate electrode shortening. By providing mechanical support and maintaining uniform gate lengths, these preliminary structures prevent the chain reaction that leads to threshold voltage instability.
Solution Approach 2:
The dummy hardmask and dummy select gate electrodes act as intermediaries that decouple the CMP process from the actual gate electrodes. This intermediary layer ensures that surface uniformity is achieved through CMP without directly impacting the gate electrode dimensions, thereby maintaining threshold voltage consistency.
3Productivity
If standard CMP process is used for planarization, then processing efficiency is maintained, but nickel contamination occurs leading to device failure
Solution Approach 1:
The dummy hardmask and dummy select gate electrode structures serve as protective intermediaries during CMP processing. These structures prevent direct contact between the CMP slurry and the actual gate electrodes, blocking the pathway for nickel contamination while still allowing the CMP process to proceed efficiently for surface planarization.
Solution Approach 2:
The patent applies beforehand cushioning by forming the dummy structures prior to CMP processing. These structures provide a protective barrier that cushions the actual gate electrodes from harmful contaminants during the CMP process, enabling efficient planarization without the risk of nickel contamination that would otherwise lead to device failure.
Data Source
AI summary
Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate including a logic region and a memory cell region. A logic device is arranged on the logic region. A memory device is arranged on the memory cell region. An isolation structure extends into a top surface of the semiconductor substrate, and laterally separates the logic region from the memory cell region. The isolation structure includes dielectric material and has an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to memory cell region.