Anti-Doped nMOS Voltage Reference for Temperature Stability
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Solution Overview
Problem
Existing voltage reference circuits in CMOS ICs face challenges in achieving high precision and compactness due to temperature variability and fabrication complexity, particularly when using MOSFETs of different polarities or flipped-gate structures, which complicate the fabrication workflow and introduce substrate noise.
Innovation Solution
The introduction of an anti-doped nMOS device, which is intrinsically matched with native nMOS devices, providing high temperature stability and suppressing substrate noise, and can be fabricated with minor adjustments to the standard CMOS workflow by modifying photolithography masks, allowing for a compact and low-power voltage reference circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If MOSFETs of different polarities or flipped-gate structures are used to achieve high precision voltage reference, then measurement precision is improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent changes the doping parameter of the MOSFET gate from conventional n-type to p-type (anti-doped), while keeping the device structure identical. This parameter change enables the use of simple nMOS devices instead of complex flipped-gate or different polarity structures, thereby maintaining voltage reference precision while significantly simplifying fabrication processes
Solution Approach 2:
The patent uses homogeneous nMOS device structures for both the reference voltage generation and comparison operations. By eliminating the need for different device types (such as pMOS or flipped-gate structures), the fabrication process is simplified while maintaining the required precision through matched device characteristics
2Stability of the object's composition
If flipped-gate structures are used to achieve temperature stability, then stability is improved, but substrate noise increases
Solution Approach 1:
The patent converts the typically harmful substrate doping into a beneficial feature by using p-type doping in the nMOS gate. This anti-doped structure inherently suppresses substrate noise while maintaining temperature stability, transforming what would normally be a source of interference into an advantage for noise rejection
3Ease of manufacture
If standard CMOS workflow is used without modifications, then ease of manufacture is maintained, but temperature variability and noise suppression are insufficient
Solution Approach 1:
The patent incorporates the p-type doping of the nMOS gate as a preliminary action during the photolithography stage. By modifying the photomask to include the gate region in the doping process, the temperature stability and noise suppression are built into the device structure from the beginning, rather than requiring additional correction steps later in fabrication
Data Source
AI summary
In a method of fabricating an electronic device, a first nMOS device structure and a second nMOS device structure are formed. Each nMOS device structure includes a gate oxide disposed on a p-type base material and a gate disposed on the gate oxide. N-type dopant implantation is performed to form source and drain regions in the p-type substate of the first nMOS device structure and source and drain regions in the p-type substate of the second nMOS device structure, and to further dope the gate of the first nMOS device structure n-type to form a first nMOS device with the gate doped n-type. P-type dopant implantation is performed to dope the gate of the second nMOS device structure p-type to form the second nMOS device structure with the gate anti-doped p-type.