Anti-Eclipse Circuit for CMOS Imager Pixel Reset Voltage Stability

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

CMOS imagers suffer from eclipsing distortion, where pixels output a dark signal even when exposed to bright light due to spillover of photogenerated charge, leading to incorrect reset and photo signals, which existing anti-eclipse circuits struggle to mitigate effectively, especially with variations in threshold voltages and temperature changes.

Innovation Solution

An improved anti-eclipse circuit is introduced, utilizing a clip circuit with a clip transistor, clamp switch, and memory capacitor to maintain the pixel reset voltage above a minimum level, incorporating a global multiplex circuit to manage voltage levels and prevent eclipsing artifacts, thereby ensuring a stable output even with threshold voltage variations and temperature changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional anti-eclipse circuit is used to mitigate eclipsing distortion, then the reset voltage can be maintained above a minimum level, but the circuit fails to account for threshold voltage variations and temperature changes, reducing reliability

Engineering Contradiction:
Improvereset voltage stabilityVSAvoidresponse to threshold voltage and temperature variations
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements a feedback mechanism where the anti-eclipse circuit continuously monitors the reset voltage level and dynamically adjusts the clip transistor gate voltage in response. When the reset voltage approaches the minimum level, the feedback loop activates to increase the clip voltage, thereby maintaining the reset voltage above the threshold. This closed-loop control ensures reliable operation under varying threshold voltage and temperature conditions.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent dynamically changes the clip voltage parameter based on operating conditions. The gate voltage of the clip transistor is adjusted in real-time according to the monitored reset voltage level, allowing the circuit to adapt to threshold voltage variations and temperature changes. This parameter adjustment enables the circuit to maintain stable reset voltage across different operating conditions.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the clip transistor gate voltage is increased to prevent eclipsing, then the reset voltage is maintained above minimum level, but photogenerated charge may spill over during integration period, causing incorrect pixel output

Engineering Contradiction:
Improvereset voltage levelVSAvoidphotogenerated charge spillover
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent employs periodic control of the clip transistor gate voltage that is synchronized with the pixel operation cycles. During the reset period, the gate voltage is increased to maintain reset voltage above minimum level. During the integration period, the gate voltage is reduced or disabled to prevent photogenerated charge spillover. This time-division control eliminates the harmful effects while preserving the beneficial reset voltage maintenance.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent dynamically adjusts the clip transistor gate voltage based on the operational phase of the pixel. The gate voltage transitions from a higher level during reset to a lower or zero level during integration, creating a dynamic control scheme that prevents charge spillover while maintaining reset voltage stability. This dynamic approach resolves the contradiction between preventing eclipsing and avoiding false signals.

Inventive Principle:
Principle #15Dynamics

3Object-affected harmful factors

If existing anti-eclipse circuits are used, then some protection against eclipsing is provided, but they struggle to mitigate distortion effectively under threshold voltage variations and temperature changes

Engineering Contradiction:
Improveeclipsing distortionVSAvoidperformance under environmental variations
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent uses feedback control to continuously monitor reset voltage and adjust clip transistor gating accordingly. This feedback mechanism enables the circuit to adapt to threshold voltage drift and temperature changes, maintaining effective eclipsing distortion mitigation under varying environmental conditions. The feedback loop ensures that the anti-eclipse function remains reliable across different operating parameters.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively maintains the pixel reset voltage above a minimum level, preventing eclipsing distortion and ensuring a wider dynamic range, regardless of threshold voltage variations and temperature changes, thereby improving the accuracy of pixel output signals.

Implementation Method 1

a light sensitive element 101, shown as a photodiode... each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode for accumulating photo-generated charge

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS7710471B2Pixel individual anti-eclipse circuit and its operation manner
Publication Date: 2010.05.04 APTINA IMAGING CORP
  • US7710471B2 patent drawing
  • US7710471B2 patent drawing
  • US7710471B2 patent drawing

AI summary

An anti-eclipse circuit of an image pixel includes a pixel coupled to a pixel output line and a circuit for receiving and storing a pixel reset voltage from the pixel on the pixel output line and for using the stored pixel reset voltage as a parameter to control a reset voltage level on the output line in a manner which maintains the pixel reset voltage on the pixel output line above a predetermined minimum voltage.