Anti-floating Circuit for IC Output Signal Stability
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Solution Overview
Problem
Integrated circuits can experience false actions and electrostatic discharge (ESD) damage due to floating output signals when input signals are not ready, leading to incorrect operations and potential damage.
Innovation Solution
An anti-floating circuit comprising a pull-high circuit, a pull-low circuit, and a control circuit, utilizing P-type and N-type transistors to manage output signals and prevent false actions by setting output signals to predetermined values during not-ready modes, thereby preventing ESD currents from reaching the core circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the integrated circuit operates without anti-floating protection, then the circuit can respond quickly to input signals, but false actions and ESD damage may occur when input signals are not ready
Solution Approach 1:
The anti-floating circuit is divided into separate functional modules: a first pull-high circuit with P-type transistors, a first pull-low circuit with N-type transistors, and a first control circuit. This segmentation allows each module to perform its specific function independently, preventing false actions while maintaining manageable circuit complexity.
Solution Approach 2:
The control circuit proactively detects when the input signal is not ready and preemptively sets the output signal to a predetermined value by controlling the pull-high and pull-low circuits. This preliminary action prevents false actions before they can occur, rather than reacting after the problem arises.
2Reliability
If the output signal is left floating when input is not ready, then the circuit maintains simplicity, but ESD currents can reach the core circuit causing damage
Solution Approach 1:
The anti-floating circuit acts as an intermediary protective layer between the input signal and the core circuit. The pull-high and pull-low circuits, controlled by the control circuit, mediate the output signal state to prevent ESD currents from reaching the core circuit when the input signal is not ready.
Solution Approach 2:
The control circuit proactively detects when the input signal is not ready and preemptively sets the output signal to a predetermined value by controlling the pull-high and pull-low circuits. This preliminary action prevents false actions before they can occur, rather than reacting after the problem arises.
3Reliability
If pull-high and pull-low circuits are always active, then the output signal is always defined, but power consumption increases
Solution Approach 1:
The pull-high and pull-low circuits are dynamically controlled rather than always active. The control circuit adjusts their states based on the input signal readiness, making them active only when needed to prevent false actions or ESD damage, thereby reducing unnecessary power consumption while maintaining output signal stability.
Data Source
AI summary
An anti-floating circuit including a first pull-high circuit, a first pull-low circuit and a first control circuit is provided. The first pull-high circuit includes a first P-type transistor and a second P-type transistor and is coupled to a first power terminal. The first pull-low circuit includes a first N-type transistor and a second N-type transistor and is coupled to a second power terminal. A first path is between the first P-type transistor and the first N-type transistor. A second path is between the second P-type transistor and the second N-type transistor. A third path is between the first P-type transistor and the second power terminal. In the first mode, the control circuit turns on the first and second paths and turns off the third path. In the second mode, the control circuit turns off the first and second paths and turns on the third path.