Anti-Fuse Cell Layout for Lower Read Current Variability
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Solution Overview
Problem
Integrated circuits (ICs) with anti-fuse bits face challenges in programming and read operations due to high parasitic path resistance and variability in read current values, primarily caused by longer gate structure segments that increase resistance and variability in current paths.
Innovation Solution
The configuration of anti-fuse cells and arrays with gate structure segments shorter than the distance between adjacent active areas, reducing parasitic path resistance and enhancing the uniformity of read current paths by positioning gate regions closer to active areas, thereby improving programming and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate structure segments are made longer to extend current paths, then the coverage area increases, but parasitic path resistance increases and read current variability worsens
Solution Approach 1:
The gate structure is divided into multiple separate gate segments, each associated with specific anti-fuse bits. By segmenting the gate structure, the patent reduces the length of individual gate segments while maintaining comprehensive coverage through multiple segments. This segmentation directly addresses the contradiction by allowing shorter gate segments (reducing parasitic resistance) while still covering the required area through the combined effect of multiple segments.
Solution Approach 2:
The patent transitions from a single-dimensional long gate structure to a multi-dimensional arrangement of multiple shorter gate segments distributed across the array. By organizing gates in rows and columns that intersect to form multiple current paths, the solution achieves area coverage through spatial distribution rather than extending individual gate lengths, thereby reducing parasitic resistance while maintaining coverage.
2Area of stationary object
If gate structure segments are made longer to extend current paths, then the coverage area increases, but parasitic path resistance increases
Solution Approach 1:
The gate structure is divided into multiple separate gate segments, each associated with specific anti-fuse bits. By segmenting the gate structure, the patent reduces the length of individual gate segments while maintaining comprehensive coverage through multiple segments. This segmentation directly addresses the contradiction by allowing shorter gate segments (reducing parasitic resistance) while still covering the required area through the combined effect of multiple segments.
Solution Approach 2:
Multiple shorter gate segments are combined to achieve the functional equivalent of a single long gate structure. By merging the effects of multiple short segments distributed across the array, the patent achieves the coverage area of a long gate while avoiding the parasitic resistance penalty, as each individual segment remains short.
3Reliability
If gate structure segments are made shorter to reduce resistance, then parasitic path resistance decreases, but coverage area reduces
Solution Approach 1:
The gate structure is divided into multiple separate gate segments, each associated with specific anti-fuse bits. By segmenting the gate structure, the patent reduces the length of individual gate segments while maintaining comprehensive coverage through multiple segments. This segmentation directly addresses the contradiction by allowing shorter gate segments (reducing parasitic resistance) while still covering the required area through the combined effect of multiple segments.
Solution Approach 2:
The patent transitions from a single-dimensional long gate structure to a multi-dimensional arrangement of multiple shorter gate segments distributed across the array. By organizing gates in rows and columns that intersect to form multiple current paths, the solution achieves area coverage through spatial distribution rather than extending individual gate lengths, thereby reducing parasitic resistance while maintaining coverage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in more reliable programming and read operations with reduced resistance and variability in read current values, leading to improved performance and consistency in anti-fuse bit operations.
Implementation Method 1
a programming electric field is applied across the dielectric material layer to sustainably alter (e.g., break down) the dielectric material, thus decreasing the resistance of the dielectric material layer
Data Source
AI summary
An IC device includes a first anti-fuse structure including a first dielectric layer between a first gate conductor and an active area, a second anti-fuse structure including a second dielectric layer between a second gate conductor and the active area, and a first pair of conductive segments electrically connected to the first and second gate conductors and aligned along a row direction perpendicular to a column direction of the first and second gate conductors. The active area is included in a plurality of active areas, the first pair of conductive segments is included in a plurality of pairs of conductive segments, and adjacent pairs of conductive segments of the plurality of pairs of conductive segments are separated by a total of two active areas of the plurality of active areas.