Anti-fuse Structure Using Segmented Dielectric Interface

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current anti-fuse structures require high programming voltages and are sensitive to thickness variations in the anti-fuse layer, leading to inconsistent programming yields and increased fabrication complexity, as they need to breach the bulk thickness of the anti-fuse layer to form a conductive link, which is not compatible with typical chip supply voltages.

Innovation Solution

An anti-fuse structure is formed by creating a conductive link at a dielectric interface rather than through a bulk dielectric, using a metallic element insulated between two Mx metal layers, allowing for programming at lower voltages and reducing the effective breakdown distance, thus enhancing reliability and integration with existing process flows.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conductive link is formed by breaching the bulk thickness of the anti-fuse layer, then a conductive path is established, but high programming voltage is required and thickness variations cause yield inconsistency

Engineering Contradiction:
Improveprogramming yield consistencyVSAvoidprogramming voltage requirement
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The anti-fuse layer is segmented into two separate anti-fuse layers with a conductive layer positioned between them. Instead of forming a single conductive link through the entire bulk thickness, the structure divides the breakdown path into two separate interfaces, each requiring lower voltage to breach. This segmentation reduces the programming voltage requirement and eliminates sensitivity to total thickness variations, as each interface's thickness can be controlled independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A conductive layer is introduced as an intermediary between the two anti-fuse layers. This conductive layer serves as a mediator that reduces the overall breakdown voltage requirement, as the conductive link forms at two separate dielectric-conductive interfaces rather than through a single thick dielectric layer. The intermediary conductive layer enables programming at lower voltages while improving yield consistency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the bulk thickness of the anti-fuse layer is breached to form a conductive link, then current flow is enabled, but fabrication complexity and costs increase

Engineering Contradiction:
Improveanti-fuse functionalityVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The formation of the conductive link is merged with the existing interconnect formation process. The conductive layer that would normally be used for interconnect purposes is simultaneously used as the conductive element in the anti-fuse structure. This merging eliminates the need for separate anti-fuse layer deposition and processing steps, reducing fabrication complexity and costs while maintaining anti-fuse functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The conductive layer serves multiple functions: it acts as both the interconnect material for signal transmission and as the conductive element for anti-fuse programming. This multi-functionality reduces the number of separate components and processing steps required, simplifying the overall fabrication process while ensuring reliable anti-fuse operation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If high programming voltage is applied to breach the anti-fuse layer, then a conductive link is formed, but the structure is incompatible with typical chip supply voltages

Engineering Contradiction:
Improveconductive link formationVSAvoidcompatibility with chip supply voltage
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The anti-fuse structure is segmented into two thinner anti-fuse layers instead of one thick layer, reducing the breakdown voltage requirement at each interface. This segmentation enables the anti-fuse to be programmed at voltages compatible with typical chip supply voltages (e.g., 1.8V or 3.3V) while still forming reliable conductive links through the dielectric-conductive interfaces.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The structure parameters are changed by introducing a conductive layer that modifies the electrical characteristics of the anti-fuse. The presence of the conductive layer changes the breakdown mechanism from requiring high voltage to breach a single thick dielectric to requiring lower voltage to breach two thinner dielectric interfaces, making the anti-fuse compatible with standard chip supply voltages.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the programming voltage and current requirements, improves yield consistency, and simplifies integration into standard semiconductor processes, enabling reliable operation at chip supply voltages while minimizing processing costs.

Implementation Method 1

programming means applying a suitable voltage to two electrodes and forming a conductive link between them to close the circuit

Methodology Applied
Scientific EffectDielectric breakdown: Avalanche Breakdown

Data Source

PatentUS8736020B2Electronic anti-fuse
Publication Date: 2014.05.27 GLOBALFOUNDRIES US INC
  • US8736020B2 patent drawing
  • US8736020B2 patent drawing
  • US8736020B2 patent drawing

AI summary

An electronic anti-fuse structure, the structure including an Mx level comprising a first Mx metal and a second Mx metal, a dielectric layer located above the Mx level, an Mx+1 level located above the dielectric layer; and a metallic element in the dielectric layer and positioned between the first Mx metal and the second Mx metal, wherein the metallic element is insulated from both the first Mx metal and the second Mx metal.