Anti-Prefetch Instruction for Transactional Execution
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Solution Overview
Problem
Multi-stranded processors face issues with transactional execution due to potential interfering memory accesses, leading to unnecessary transaction failures and inefficiencies in parallel code execution.
Innovation Solution
The introduction of an anti-prefetch instruction that stalls subsequent instruction decoding unless a cache line contains a predetermined value, allowing for conditional execution and re-execution based on cache line contents, thereby preventing unnecessary transaction failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the second strand transactionally loads from the mailbox before the first strand stores the predetermined value, then the second strand can proceed with transactional execution, but the cache line is load-marked causing the first strand to erroneously detect interfering access and fail the transaction
Solution Approach 1:
The anti-prefetch instruction performs a preliminary check of the cache line contents before the actual transactional load occurs. By checking if the mailbox contains the predetermined value in advance, the system prevents the load-marking operation from occurring when it would cause false interference detection, thus maintaining both parallel execution efficiency and transaction reliability
Solution Approach 2:
The anti-prefetch instruction acts as an intermediary between the first strand's store operation and the second strand's load operation. It mediates the interaction by checking cache line contents and conditionally preventing the problematic load-marking operation, allowing both strands to execute in parallel without false interference detection
2Reliability
If the processor uses a spin loop technique with transactional loading to ensure first strand completion, then transaction atomicity is maintained, but unnecessary transaction failures occur due to false interference detection
Solution Approach 1:
The anti-prefetch instruction performs a preliminary check of the cache line contents before the transactional load occurs. By checking if the mailbox contains the predetermined value in advance, the system prevents the load-marking operation from occurring when it would cause false interference detection, thus maintaining both parallel execution efficiency and transaction reliability
Solution Approach 2:
The system changes the parameter of cache line marking by conditionally preventing the load-mark operation when the anti-prefetch check indicates the mailbox does not yet contain the predetermined value. This parameter change (whether or not to mark the cache line) resolves the contradiction between maintaining atomicity and avoiding false interference detection
Data Source
AI summary
Embodiments of the present invention execute an anti-prefetch instruction. These embodiments start by decoding instructions in a decode unit in a processor to prepare the instructions for execution. Upon decoding an anti-prefetch instruction, these embodiments stall the decode unit to prevent decoding subsequent instructions. These embodiments then execute the anti-prefetch instruction, wherein executing the anti-prefetch instruction involves: (1) sending a prefetch request for a cache line in an L1 cache; (2) determining if the prefetch request hits in the L1 cache; (3) if the prefetch request hits in the L1 cache, determining if the cache line contains a predetermined value; and (4) conditionally performing subsequent operations based on whether the prefetch request hits in the L1 cache or the value of the data in the cache line.