Anti-ferroelectric Buffer Layer for FeFET Metal Migration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in maintaining the performance and reliability of ferroelectric field effect transistor (FeFET) devices due to metal migration and interface trap formation between ferroelectric and metal-containing layers, which degrades device performance.
Innovation Solution
Incorporating anti-ferroelectric layers adjacent to ferroelectric layers to act as a buffer, suppressing metal migration and interface trap formation, and controlling the composition and thickness of these layers to optimize device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal-containing layers are deposited adjacent to ferroelectric layers to form FeFET devices, then device functionality is achieved, but metal migration and interface trap formation occur which degrade device performance
Solution Approach 1:
An anti-ferroelectric buffer layer is introduced between the metal-containing layer and the ferroelectric layer. This intermediary layer suppresses metal migration from the metal-containing layer into the ferroelectric layer and reduces interface trap formation, thereby protecting the ferroelectric layer while maintaining device functionality.
Solution Approach 2:
The device structure employs a composite material approach by combining anti-ferroelectric and ferroelectric materials in a layered configuration. The anti-ferroelectric buffer layer (containing Hf, Zr, and Si) is deposited adjacent to the ferroelectric layer (containing Hf, Zr, and Si), creating a composite structure that leverages the beneficial properties of both material types to improve overall device reliability.
2Productivity
If the ferroelectric layer is made thinner to improve device scaling, then device density increases, but metal migration and interface defects have a greater relative impact on performance
Solution Approach 1:
The anti-ferroelectric buffer layer serves as a protective intermediary that becomes increasingly important as the ferroelectric layer thickness is reduced for scaling. This buffer layer effectively suppresses metal migration and interface trap formation even in ultra-thin ferroelectric layers, enabling continued device scaling while maintaining reliability.
3Reliability
If anti-ferroelectric buffer layers are added to suppress metal migration, then device reliability improves, but device structure complexity increases
Solution Approach 1:
The anti-ferroelectric buffer layer is designed with specific compositional parameters (Hf, Zr, and Si content ratios) and thickness parameters (optimized to be thin, typically 1-10 nm) that allow it to provide effective protection against metal migration while minimizing the increase in overall device complexity. The layer is engineered with precise parameter control to achieve the desired protective function with minimal structural addition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The anti-ferroelectric layers enhance the reliability and performance of FeFET devices by reducing metal diffusion and interface defects, leading to improved device stability and functionality.
Implementation Method 1
the first anti-ferroelectric layer is to provide a barrier to migration of the components of the conductive channel into the ferroelectric layer
Implementation Method 2
improve the interface configuration between the conductive channel and the anti-ferroelectric material/memory layer formed on the conductive channel
Data Source
AI summary
Some embodiments of a method for manufacturing integrated circuits include the operations of forming a back gate structure on a substrate, forming a memory layer over the back gate structure, forming a buffer layer over the memory layer, forming a conductive channel over the buffer layer, and forming source/drain regions over the conductive channel. In some embodiments, a second buffer layer is formed between the back gate structure and the memory layer.