Antiferroelectric High-k MIM Capacitor for CMOS Integration
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Solution Overview
Problem
Current integrated circuits face limitations in achieving high capacitance values in capacitors due to constraints in dielectric materials and leakage currents, leading to reliability issues and the need for external passive components, especially when using antiferroelectric materials that are not compatible with semiconductor manufacturing environments.
Innovation Solution
The integration of an antiferroelectric phase dielectric layer in MIM/MIS capacitors, formed by depositing an amorphous high-k dielectric material layer and inducing crystallization, allows for higher capacitance densities while avoiding material compatibility issues and reducing voltage drops, enabling efficient charge storage without dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials are used in capacitors, then leakage current is reduced, but capacitance value is limited
Solution Approach 1:
The patent changes the dielectric constant parameter by using high-k dielectric materials (k>10, preferably k>20) instead of conventional materials. This parameter change enables achieving higher capacitance values while maintaining acceptable leakage characteristics, directly resolving the contradiction between limited capacitance and reliability
Solution Approach 2:
The patent employs composite material structures combining high-k dielectric layers with specific electrode configurations. This composite approach allows utilizing the high capacitance density of high-k materials while managing their inherent leakage issues through proper material stacking and interface engineering
2Quantity of substance
If high-k dielectric materials are used to increase capacitance, then capacitance density is improved, but material compatibility with semiconductor manufacturing is worsened
Solution Approach 1:
The patent selects high-k dielectric materials with specific properties (k>10) that balance capacitance enhancement with manufacturability. By carefully choosing materials whose deposition and processing parameters align with existing CMOS fabrication capabilities, the patent achieves high capacitance density without compromising ease of manufacture
Solution Approach 2:
The patent applies high-k dielectric materials in specific local regions where capacitance enhancement is most needed, rather than universally replacing all dielectrics. This localized application allows achieving high capacitance density in critical areas while maintaining compatibility with standard manufacturing processes in other regions
3Quantity of substance
If antiferroelectric materials are used to achieve high capacitance, then capacitance value is improved, but reliability due to dielectric breakdown is worsened
Solution Approach 1:
The patent uses composite material structures that combine antiferroelectric high-k materials with other dielectric layers or electrode configurations. This composite approach harnesses the high capacitance of antiferroelectric materials while the additional layers provide protection against dielectric breakdown, simultaneously improving capacitance value and reliability
Solution Approach 2:
The patent incorporates protective layers or design features beforehand that cushion against potential dielectric breakdown events. This preventive approach allows utilizing antiferroelectric materials for high capacitance while mitigating their reliability risks through pre-engineered protection mechanisms
4Area of stationary object
If capacitor size is reduced for compact design, then device area is reduced, but capacitance value is worsened
Solution Approach 1:
The patent changes the dielectric constant parameter by using high-k materials (k>10), which enables achieving the same capacitance value in a smaller area. This parameter change directly resolves the contradiction between compact design and capacitance maintenance, allowing significant area reduction while preserving capacitance
Solution Approach 2:
The patent transitions from planar capacitor designs to vertically stacked or three-dimensional capacitor structures. This dimensional change allows achieving high capacitance values in reduced footprint areas by utilizing the third dimension, effectively resolving the area-capacitance trade-off for compact designs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables integrated circuits to achieve higher capacitance values with lower voltage drops, enhancing reliability and allowing for compact designs without the need for external components, while being compatible with CMOS processes.
Implementation Method 1
a dielectric layer formed over a surface of the substrate, and an electrode layer formed over the dielectric layer, wherein the dielectric layer is in an antiferroelectric phase
Implementation Method 2
depositing an amorphous high-k dielectric material layer on the substrate
Implementation Method 3
inducing crystallization in the amorphous high-k dielectric material layer, the crystallized high-k dielectric material layer being in an antiferroelectric phase
Data Source
AI summary
The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.