Anti-fuse Device with Anti-Breakdown Layer for Current Distribution
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing chip size and cost while improving current distribution characteristics, particularly in anti-fuse devices used for redundancy programming and option programming.
Innovation Solution
Incorporation of an anti-breakdown material layer between junction regions and a gate insulating layer in the anti-fuse device, which can be made of silicon oxide, silicon nitride, or silicon oxynitride, to control breakdown and reduce power consumption during programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional anti-fuse device structure is used, then chip size can be reduced, but current distribution characteristics deteriorate and power consumption increases
Solution Approach 1:
An anti-breakdown material layer is introduced as an intermediary between the gate insulating layer and the substrate. This layer mediates the electrical breakdown process by controlling the electric field distribution, preventing excessive current concentration while enabling controlled breakdown for programming operations, thus reducing power consumption without increasing chip size
Solution Approach 2:
The electrical characteristics of the anti-fuse device are modified by changing the material parameters of the gate insulating layer (using high-k materials) and introducing the anti-breakdown material layer. These parameter changes enable better current distribution characteristics and reduced power consumption while maintaining the compact device structure
2Ease of manufacture
If conventional gate insulating layer is used, then manufacturing process is simple, but breakdown characteristics are poor leading to higher power consumption
Solution Approach 1:
The gate insulating layer is formed as a composite structure combining a first insulating material layer (conventional material such as silicon oxide) and a second insulating material layer (high-k material). This composite structure achieves superior breakdown characteristics and controlled electrical properties while remaining compatible with existing manufacturing processes
Solution Approach 2:
The anti-breakdown material layer serves as an intermediary between the gate insulating layer and substrate, controlling the breakdown process. This intermediary layer prevents uncontrolled breakdown while maintaining manufacturing simplicity by using standard deposition techniques
3Loss of energy
If additional process steps are added to improve current distribution, then current dispersion characteristics improve, but manufacturing complexity and cost increase
Solution Approach 1:
The formation of the gate insulating layer and anti-breakdown material layer is merged with existing manufacturing processes. The anti-breakdown material layer is formed simultaneously with or integrated into the gate insulating layer formation process, eliminating the need for separate additional process steps while achieving improved current distribution characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reduced chip size and cost, with improved current dispersion characteristics and narrower distribution of device characteristics between broken-down anti-fuses, leading to lower power consumption and enhanced programming efficiency.
Implementation Method 1
an anti-fuse device, which is an electronic device capable of converting a nonconductive state into a conductive state, may be used for a redundancy programming or option programming in response to a programming voltage (or current) and electrical stress
Data Source
AI summary
An anti-fuse device includes a gate electrode on a semiconductor substrate, a gate insulating layer between the semiconductor substrate and the gate electrode, junction regions in the semiconductor substrate adjacent the gate electrode, and at least one anti-breakdown material layer between the junction regions, the gate insulating layer being between the gate electrode and the anti-breakdown material layer.


