Anti-Fuse Cell Array Stacking for Compact DRAM Repair Circuits
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Solution Overview
Problem
The increasing complexity of memory devices with vertical channel transistors and core peripheral circuits leads to a significant increase in chip size, necessitating a reduction in the area occupied by repair circuits to improve the storage capacity and integration of DRAM chips.
Innovation Solution
Incorporating an anti-fuse cell array in a separate area within the cell array structure, allowing for a repair circuit that controls and programs anti-fuse cells to replace defective memory cells with redundancy cells, thereby reducing the core peripheral circuit area and chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical channel transistors and core peripheral circuits are integrated to improve storage capacity and operational speed, then memory device performance is enhanced, but chip size increases significantly
Solution Approach 1:
The patent implements a three-dimensional stacked architecture where the cell array structure is positioned vertically above the core peripheral circuit structure. This vertical stacking approach transitions from a planar two-dimensional layout to a three-dimensional configuration, allowing both high-capacity memory cells and essential peripheral circuits to coexist on the same chip without increasing lateral footprint, thereby resolving the contradiction between enhanced storage capacity and controlled chip size.
Solution Approach 2:
The cell array structure is nested above the core peripheral circuit structure in a vertical arrangement, with the bonding metal pad enabling electrical connection between the two stacked structures. This nesting configuration allows the memory device to integrate both high-capacity storage functionality and peripheral circuit operations within a compact footprint, effectively addressing the chip size expansion issue while maintaining improved productivity.
2Area of stationary object
If core peripheral circuit area is reduced to minimize chip size, then manufacturing efficiency improves, but repair circuit functionality may be compromised
Solution Approach 1:
The repair circuit is integrated within the cell array structure in the vertical dimension rather than occupying lateral space in the core peripheral circuit area. By positioning the repair circuit in the stacked configuration above the core peripheral circuits, the patent enables reduced core peripheral circuit area while preserving complete repair circuit functionality through this three-dimensional spatial arrangement.
Solution Approach 2:
The bonding metal pad structure is replicated across multiple bonding interfaces to enable both data transmission and repair operations. This copying approach allows the repair circuit to function independently within the cell array structure while sharing bonding infrastructure with the core peripheral circuits, thereby maintaining full repair functionality despite reduced core peripheral circuit area.
Data Source
AI summary
Provided is a memory device including an anti-fuse cell array in a cell array structure. The memory device includes a core peripheral circuit structure including a first bonding metal pad, and a cell array structure arranged above the core peripheral circuit structure and including a second bonding metal pad in contact with the first bonding metal pad. The cell array structure includes a plurality of memory blocks and a plurality of anti-fuse cells. The core peripheral circuit structure further includes a repair circuit connected to the anti-fuse cells, and the repair circuit is configured to control each anti-fuse cell to be programmed, and perform, based on fuse data of the anti-fuse cells received through the first and second bonding metal pads connected to the anti-fuse cells, a repair operation of replacing a defective memory cell in the memory cell array area with a redundancy memory cell.