Anti-fuse Array Post-Packaging Repair via Gate Dielectric Breakdown
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Solution Overview
Problem
Conventional semiconductor device repair processes face challenges with high error rates after packaging, as existing fuses are designed for disconnection and are difficult to use post-packaging, necessitating a new type of fuse that can perform interconnection for effective repair.
Innovation Solution
An anti-fuse array is developed, comprising a semiconductor substrate with specific impurity implantation regions and a gate electrode structure that allows for the formation of a PN junction, enabling rupture of the gate insulation film under a potential difference, creating a current path for repair without requiring a select transistor, thus allowing for efficient post-packaging repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of repair
If an anti-fuse structure is implemented for post-packaging repair, then interconnection-based repair is enabled, but device complexity increases
Solution Approach 1:
The patent merges the anti-fuse repair mechanism with the existing memory cell structure. The anti-fuse is formed using the same transistor architecture and material layers as the functional cells, integrating the repair capability into the existing device without adding separate complex repair circuits.
Solution Approach 2:
The anti-fuse structure serves multiple functions: it acts as a functional memory cell during normal operation and as a repair mechanism when activated. The same physical structure provides both storage functionality and repair capability, reducing overall device complexity.
2Ease of repair
If redundant cells are added for repair purposes, then repair capability is improved, but area occupation increases
Solution Approach 1:
The patent applies local quality by creating anti-fuses with specific structural characteristics in the periphery region. The anti-fuses in the repair array have optimized dimensions and doping profiles tailored for reliable breakdown and interconnection, while the functional cells maintain their original design for storage operations.
Solution Approach 2:
The patent utilizes the vertical dimension by forming the anti-fuse structure with a gate electrode and insulator layer stack, creating the conductive path through vertical breakdown rather than lateral connection. This three-dimensional approach to creating the repair path reduces the horizontal area required for the repair mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The anti-fuse array effectively reduces error rates by enabling reliable post-packaging repair with minimal area occupation, improving product characteristics and yield by allowing interconnection instead of disconnection, overcoming limitations of conventional fuses.
Implementation Method 1
When a potential difference between the second-type impurity implantation region and the channel region is equal to or higher than a predetermined potential difference, the gate insulation film may be ruptured
Implementation Method 2
a first junction region serving as a channel region... a second junction region doped with a second dopant and configured to form a PN junction with the first junction region
Data Source
AI summary
An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.