Anti-Fuse Array Layout With Shared Programming Gate Lines
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Solution Overview
Problem
The current anti-fuse arrays have a relatively low integration level, which is a challenge as semiconductor devices continue to shrink in size and increase in density.
Innovation Solution
The anti-fuse array design includes first and second active areas with specific spacing and orientation, allowing second active areas to be positioned between end portions of adjacent first active areas, utilizing spare space and sharing programming gate lines, thereby increasing integration level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional anti-fuse array layout is used, then manufacturing is simpler, but integration level is low
Solution Approach 1:
The patent merges the programming gate lines by making them shared between multiple active areas. Specifically, a programming gate line covers programming regions in different active areas, reducing the total number of programming gate lines needed and thereby improving integration level while maintaining manufacturability
Solution Approach 2:
The patent optimizes the spatial arrangement of active areas by positioning second active areas between end portions of adjacent first active areas. This staggered layout in the first direction, combined with extension in the second direction, creates more efficient space utilization and improves integration level
2Adaptability or versatility
If more programming gate lines are used, then each active area can be independently programmed, but device complexity increases
Solution Approach 1:
The programming gate lines are designed to serve multiple functions by being shared across different active areas. Each programming gate line can control programming operations in multiple programming regions, reducing the total number of gate lines while maintaining the ability to independently program different active areas through selective activation
Solution Approach 2:
Multiple programming gate lines are merged into shared gate lines that span across multiple active areas. The shared programming gate line structure allows a single gate line to control multiple programming regions, thereby reducing device complexity while preserving programming versatility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances space utilization and integration level of anti-fuse circuits by optimizing the layout and reducing the number of programming gate lines, while maintaining electrical isolation and performance.
Implementation Method 1
After programming, the insulating dielectric layer is broken down, such that the anti-fuse memory is in a low-resistance state
Data Source
AI summary
Embodiments relate to an anti-fuse array and a memory. The anti-fuse array includes: a column of first active areas, where each of the first active areas includes a first channel region, a first source/drain region and a second source/drain region, and a first programming region; a column of second active areas, where each of the second active areas includes a second channel region, a third source/drain region and a fourth source/drain region, and a second programming region, an end portion, close to the first active areas, of the given second active area directly faces a region between end portions, close to the given second active area, of two adjacent first active areas; a first gate line; a second gate line covering each second channel region in a column of the second active areas; and a programming gate line.