Anti-Fuse Cell Buried Rail Layout for Higher Read Current
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Solution Overview
Problem
Current anti-fuse memory cells face limitations in reducing resistance during program and read operations, which affects the efficiency of data storage and retrieval due to high resistances in the interconnect layers and bit lines.
Innovation Solution
The solution involves burying the bit line within the substrate as a buried rail, eliminating the RMG resistance and reducing the overall resistance in the path of the read current, thereby increasing the read and program currents by optimizing the layout and interconnects of the anti-fuse cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the bit line is routed through interconnect layers above the active region, then the layout is simpler and easier to manufacture, but the resistance in the path of the read current increases due to RMG resistance
Solution Approach 1:
The bit line is moved from the horizontal plane (interconnect layer) to the vertical dimension by forming it as a buried rail within the substrate below the active region. This dimensional transition eliminates the RMG resistance that occurs when current flows through the interconnect layer, thereby improving read current reliability while maintaining manufacturing feasibility through standard substrate processing techniques.
2Reliability
If the bit line is buried within the substrate as a buried rail, then the resistance in the path of the read current is reduced, but the layout complexity and manufacturing process difficulty increase
Solution Approach 1:
The bit line is merged with the substrate structure by forming it as a buried rail within the substrate itself, rather than as a separate interconnect layer. This integration eliminates the need for additional routing layers and vias, reducing layout complexity while achieving the goal of lowering resistance and improving read current reliability.
Data Source
AI summary
A memory device includes an anti-fuse cell array having a plurality of anti-fuse cells, each of the plurality of anti-fuse cells having a first transistor and a second transistor connected to the first transistor. A first terminal of the first transistor is connected to a bit line and the bit line is a buried rail formed in a substrate of the first transistor and the second transistor.