Anti-Fuse Memory Cell Layout for Lower Gate Path Resistance
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Solution Overview
Problem
Existing anti-fuse memory technologies face challenges in optimizing the resistance path between the program word line and the gate of the transistor, leading to inefficiencies in programming and reading operations.
Innovation Solution
The proposed solution involves optimizing the layout of anti-fuse memory cells by positioning gate vias directly above the active areas, which reduces the equivalent resistance on the current path and enhances operational performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate vias are positioned away from active areas in conventional anti-fuse memory layout, then manufacturing is easier and design rules are simpler to follow, but the equivalent resistance on the current path increases leading to slower operation speed
Solution Approach 1:
The patent positions gate vias in the vertical dimension directly above active areas rather than horizontally adjacent, utilizing the third dimension (depth) to optimize current path resistance without increasing lateral footprint or violating planar design rules
Solution Approach 2:
The patent applies different via positioning strategies for different components: gate vias are positioned directly above active areas to minimize resistance, while other vias follow conventional placement, creating localized optimization without requiring complete layout redesign
2Productivity
If gate vias are positioned directly above active areas, then the equivalent resistance on the current path is reduced improving operation speed, but the layout becomes more complex and challenging to manufacture
Solution Approach 1:
The invention utilizes the vertical dimension for via placement, allowing gate vias to be positioned directly above active areas in the depth direction while maintaining standard lateral spacing, thereby reducing resistance without complicating the manufacturing process
Solution Approach 2:
The patent changes the positional parameter of gate vias from horizontal adjacency to vertical alignment, optimizing the current path geometry to reduce equivalent resistance while maintaining compatibility with existing fabrication capabilities
3Reliability
If conventional layout is used with gate vias positioned away from active areas, then manufacturing is simpler, but the resistance on current path increases reducing programming and reading efficiency
Solution Approach 1:
The patent optimizes the geometric parameters of the current path by positioning gate vias directly above active areas, reducing the path length and equivalent resistance, thereby minimizing energy loss while preserving data retention reliability through maintained structural integrity
Data Source
AI summary
A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.