Anti-Fuse Memory Cell Channel Width Split for Yield and Read Window
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Solution Overview
Problem
Existing anti-fuse memory cells in integrated circuits face challenges in improving programming yield and reading window size due to limitations in gate dielectric area and driving current.
Innovation Solution
The memory device incorporates anti-fuse memory cells with programming transistors having narrower nanostructure channels and reading transistors with wider nanostructure channels, enhancing the contact area of gate dielectrics and driving current respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate dielectric area is increased to improve programming yield, then the programming yield is improved, but the device area increases
Solution Approach 1:
The patent applies local quality by creating different channel widths for programming and reading operations within the same memory cell. The programming transistor has a first channel width optimized for breakdown programming, while the reading transistor has a second channel width optimized for reading current. This local differentiation allows each operation to have optimal parameters without compromising the other, resolving the contradiction between programming yield and device area.
Solution Approach 2:
The patent implements dynamics by using voltage-controlled channel behavior. The programming transistor operates in breakdown mode during programming (requiring high voltage to break down the gate dielectric) and in normal transistor mode during reading. The reading transistor operates in normal mode for both programming and reading. This dynamic operation allows the same physical structure to serve different functions at different times, improving programming yield without permanently increasing device area.
2Power
If the channel width is increased to improve driving current for reading, then the reading window is enlarged, but the programming yield decreases
Solution Approach 1:
The patent applies local quality by creating different channel widths for programming and reading operations within the same memory cell. The programming transistor has a first channel width optimized for breakdown programming, while the reading transistor has a second channel width optimized for reading current. This local differentiation allows each operation to have optimal parameters without compromising the other, resolving the contradiction between programming yield and device area.
3Area of stationary object
If the gate dielectric area is reduced to shrink device area, then the device area is reduced, but the programming yield deteriorates
Solution Approach 1:
The patent applies local quality by creating different channel widths for programming and reading operations within the same memory cell. The programming transistor has a first channel width optimized for breakdown programming, while the reading transistor has a second channel width optimized for reading current. This local differentiation allows each operation to have optimal parameters without compromising the other, resolving the contradiction between programming yield and device area.
4Reliability
If the channel width is reduced to improve programming yield, then the programming yield is improved, but the driving current for reading decreases
Solution Approach 1:
The patent applies local quality by creating different channel widths for programming and reading operations within the same memory cell. The programming transistor has a first channel width optimized for breakdown programming, while the reading transistor has a second channel width optimized for reading current. This local differentiation allows each operation to have optimal parameters without compromising the other, resolving the contradiction between programming yield and device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves programming yield and enlarges the reading window, enabling better differentiation between logic states and enhancing the overall performance of the memory device.
Implementation Method 1
A gate dielectric of the programming MOS transistor may be broken down to cause the gate and the source or drain sub-feature of the programming MOS transistor to be interconnected
Data Source
AI summary
A memory device includes a programming transistor and a reading transistor of an anti-fuse memory cell. The programming transistor includes first semiconductor nanostructures vertically spaced apart from one another, each of the first semiconductor nanostructures having a first width along a first lateral direction. The reading transistor includes second semiconductor nanostructures vertically spaced apart from one another, each of the second semiconductor nanostructures having a second width different from the first width along the second direction. The memory device also includes a first and a second gate metals. The first gate metal wraps around each of the first semiconductor nanostructures with a first gate dielectric disposed therein. The second gate metal wraps around each of the second semiconductor nanostructures with a second gate dielectric disposed therein.