Anti-Fuse Circuit Wiring for Reading Accuracy
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Solution Overview
Problem
Conventional semiconductor devices with anti-fuse elements face challenges in maintaining reading accuracy due to parasitic resistance in wiring, which affects the reliability of information storage and retrieval.
Innovation Solution
The semiconductor device incorporates a transistor, an anti-fuse element, and a resistor element connected in parallel, with a shorter electric path between the transistor and the anti-fuse element compared to the resistor element, ensuring a lower resistance for the wiring connecting the transistor and anti-fuse element, thereby enhancing reading reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional wiring layout is used connecting the transistor and anti-fuse element, then the device structure is simple, but the parasitic resistance in the wiring increases, degrading reading accuracy
Solution Approach 1:
The patent applies local quality by creating different wiring path lengths for different functional purposes: a short wiring path between the transistor and anti-fuse element for low parasitic resistance (high reliability), and a longer wiring path to the resistor element for creating sufficient resistance difference (high measurement precision). This localized differentiation of wiring characteristics resolves the contradiction between reliability and measurement precision.
Solution Approach 2:
The patent employs asymmetry by deliberately designing unequal wiring path lengths in the circuit layout. The wiring connecting the transistor to the anti-fuse element is made significantly shorter than the wiring to the resistor element, creating an asymmetric structure that generates different parasitic resistance values. This asymmetry is essential for achieving both high reading reliability (low parasitic resistance) and high measurement precision (large resistance difference).
2Reliability
If the wiring path between transistor and anti-fuse element is made shorter, then parasitic resistance decreases improving reading reliability, but the layout complexity increases
Solution Approach 1:
The patent merges the anti-fuse element and resistor element into a common circuit structure connected to the same transistor, with both elements sharing part of the wiring infrastructure. This merging approach allows the short wiring path to the anti-fuse element to be integrated efficiently into the overall layout, reducing the impact of layout complexity while achieving low parasitic resistance for high reading reliability.
Data Source
AI summary
A semiconductor device includes a transistor connected to a terminal having a first potential, an anti-fuse element connected between the transistor and a terminal having a second potential different from the first potential, and a resistor element connected in parallel with the anti-fuse element. An electric path between the transistor and the anti-fuse element has a length smaller than a length of an electric path between the transistor and the resistor element.