Anti-Fuse Structure Using Contact-Level Dielectric Breakdown
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Solution Overview
Problem
The reliability and operation margin of traditional anti-fuses in semiconductor integrated circuits are compromised due to down-scaling, particularly in FinFET and gate-all-around devices, where gate oxide thickness is insufficient for high programming voltages, and process changes at FEOL and MEOL affect their performance.
Innovation Solution
A new type of anti-fuse with a breakdown path from a source/drain contact via to a source/drain electrode, utilizing an insulator at the source/drain contact level and epitaxially-grown, heavily-doped semiconductor, allowing for a thicker insulator and higher programming voltage, ensuring reliable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional anti-fuse structures are used with down-scaled transistors, then device density and integration are improved, but reliability and operation margin deteriorate due to insufficient gate oxide thickness for high programming voltages
Solution Approach 1:
The invention transitions from a planar gate-to-channel breakdown path to a vertical gate-to-drain breakdown path in FinFET structures. This dimensional change in the breakdown trajectory allows the utilization of the fin's vertical structure, enabling higher programming voltages to be applied across the drain region rather than through the thin gate oxide, thereby resolving the contradiction between device scaling and programming voltage requirements
Solution Approach 2:
The invention changes the breakdown voltage parameter by utilizing the drain region as the breakdown target instead of the gate oxide. The heavily-doped drain region can withstand higher voltages, and by configuring the breakdown path to terminate at the drain, the anti-fuse can be programmed with higher voltages (e.g., 5V or higher) without risking gate oxide damage, thus improving reliability while maintaining scaled dimensions
2Length of stationary object
If gate oxide thickness is reduced for scaling, then geometry size decreases, but the ability to withstand programming voltage deteriorates
Solution Approach 1:
The invention extracts the breakdown target from the gate oxide region and relocates it to the drain region. By taking the breakdown function out of the gate oxide, the thin gate oxide can maintain its scaled thickness for high-density integration while the breakdown event occurs in the drain region which has sufficient voltage tolerance, thus decoupling the two conflicting requirements
Solution Approach 2:
The invention introduces the drain region as an intermediary structure that mediates between the gate and the breakdown path. The drain region, with its heavily-doped configuration, serves as an intermediate zone that can handle high programming voltages without damaging the thin gate oxide, effectively protecting the gate oxide while enabling high-voltage programming
3Ease of manufacture
If breakdown path is from gate to channel or drain in traditional transistors, then anti-fuse functionality is achieved, but resistance variation and operation margin worsen with scaling
Solution Approach 1:
The invention applies local quality by creating a heavily-doped drain region with specific properties tailored for breakdown tolerance. This localized doping enhancement in the drain region provides high voltage withstand capability and consistent breakdown characteristics, reducing resistance variation while maintaining ease of manufacture through standard CMOS-compatible processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new anti-fuse design provides reliable programming with a higher programming voltage, improving the resistance change detectability and integrating seamlessly into existing manufacturing processes.
Implementation Method 1
an insulator disposed laterally between the first and second source/drain contacts; a width of the insulator is configured such that a programming potential applied across the source/drain contact via and the drain terminal of the second transistor causes the insulator to break down
Data Source
AI summary
A structure includes first and second transistors where each of the first and the second transistors has a source terminal, a drain terminal, and a gate terminal; a first source/drain contact disposed on the source terminal of the first transistor; a second source/drain contact disposed on the drain terminal of the second transistor; an insulator disposed laterally between the first and the second source/drain contacts; a source/drain contact via disposed on the first source/drain contact; and a line connected to the source/drain contact via, wherein a width of the insulator is configured such that a programming potential applied across the source/drain contact via and the drain terminal of the second transistor causes the insulator to break down.