Anti-fuse Memory Coupling Channel Leakage Prevention
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Solution Overview
Problem
The integration of memory devices in semiconductor technology faces challenges with current anti-fuse memory devices due to current leakage between memory cells, leading to data misinterpretation and reduced reliability, particularly as line widths decrease.
Innovation Solution
The implementation of a coupling channel structure in anti-fuse memory cells, where a coupling gate separates the anti-fuse structure and doped region, allowing for controlled formation of a channel region through a fringe field effect when voltages are applied, preventing current leakage and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory devices are integrated with smaller line widths to increase integration density, then productivity and integration are improved, but current leakage between memory cells increases leading to data misinterpretation and reduced reliability
Solution Approach 1:
The patent introduces a coupling gate structure that segments the channel region into distinct sections. The coupling gate is positioned between the bit line doped region and the anti-fuse gate, creating a separated channel structure. This segmentation allows independent control of different channel regions, enabling the formation of a coupling channel that connects to the anti-fuse layer breakdown location while isolating it from the bit line, thereby preventing current leakage between adjacent memory cells.
Solution Approach 2:
The coupling gate acts as an intermediary structure between the bit line doped region and the anti-fuse gate. By applying voltages to the coupling gate and anti-fuse gate, a coupling channel is formed through the substrate that is mediated by the coupling gate structure. This intermediary coupling channel provides a controlled path for current flow during programming operations while preventing direct current leakage between the bit line and adjacent cells, thus resolving the reliability issue.
2Reliability
If a coupling gate structure is introduced to prevent current leakage, then reliability is improved, but device complexity increases
Solution Approach 1:
The coupling gate structure serves multiple functions: it defines the channel region, forms the coupling channel through fringe field effect when voltages are applied, and controls the breakdown location of the anti-fuse layer. By making the coupling gate multi-functional, the patent achieves reliable current leakage prevention without proportionally increasing device complexity, as a single structure performs multiple critical roles in the memory cell operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents current leakage and improves the reliability of anti-fuse memory devices by controlling the breakdown location of the anti-fuse layer, enabling high integration and reliable operation.
Implementation Method 1
a voltage is applied to a coupling gate and an anti-fuse gate so as to form a coupling channel in a substrate between the anti-fuse gate and the coupling gate through a fringe field effect
Data Source
AI summary
An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate.