Antifuse Memory Decoder Circuit Merging for Chip Area Reduction
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Solution Overview
Problem
The existing semiconductor memory devices face challenges with the large occupation dimension of decoder circuits due to the need for separate decoder circuits for each antifuse element, which increases chip size and complexity, especially when using antifuse elements for storing defective addresses.
Innovation Solution
Assigning a program voltage line for each nonvolatile memory element and using a decoder circuit to simultaneously apply the program voltage to all elements, with a suppression circuit to ensure consistent voltage supply even if one element fails to break down, allowing multiple nonvolatile memory elements to share a single decoder circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate decoder circuits are assigned to each antifuse element to ensure reliable programming, then programming reliability is improved, but device complexity and chip dimension increase
Solution Approach 1:
Multiple antifuse elements (AF1, AF2, AF3, AF4) share a common decoder circuit (160) and common program voltage line (16c), merging previously separate decoder assignments into a single shared resource that serves all elements simultaneously
Solution Approach 2:
The single decoder circuit (160) performs multiple functions by controlling different antifuse elements through separate driver circuits (162A, 162B), enabling one decoder to universally manage programming operations for all antifuse elements in the set
2Reliability
If separate decoder circuits are assigned to each antifuse element, then programming control is improved, but area of stationary object increases
Solution Approach 1:
Multiple antifuse elements share a common decoder circuit and common program voltage line, merging previously separate decoder assignments into a single shared resource that serves all elements simultaneously, thereby reducing the area occupied by decoder circuits
Solution Approach 2:
The patent introduces separate driver circuits (162A, 162B) as an intermediate control layer between the single decoder circuit and multiple antifuse elements, adding a dimensional layer of control that enables one decoder to manage multiple elements without requiring multiple decoders
3Device complexity
If a common program voltage line is shared by multiple antifuse elements, then device complexity is reduced, but voltage consistency may deteriorate
Solution Approach 1:
The common program voltage line (16c) is segmented into separate program voltage lines (16a, 16b) that branch to different antifuse element groups, with each segment equipped with its own driver circuit to independently control and maintain voltage consistency for served elements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of required decoder circuits, decreases chip dimension, and ensures reliable programming by maintaining sufficient program voltage across all elements, enhancing memory stability and reducing the risk of failed insulation breakdown.
Implementation Method 1
The antifuse element is in a nonconductive state in an initial state and is changed to a conductive state with an insulation-breakdown by an application of a high voltage
Data Source
AI summary
A bit memory circuit of an antifuse element set includes two antifuse elements of which logical states are changed from an insulation state to a conductive state when a program voltage is applied. 1-bit data is represented by the logical states of the two antifuse elements. The two antifuse elements are collectively controlled by one decoder circuit. When writing data, the decoder circuit simultaneously performs insulation-breakdown on the two antifuse elements by simultaneously connecting the two antifuse elements to program voltage lines, respectively.