Anti-Fuse Dielectric Layer Layout for Lower Programming Voltage
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Solution Overview
Problem
The high programming voltage of anti-fuse device structures in semiconductor structures due to thick dielectric layers.
Innovation Solution
A semiconductor structure design that includes a first dielectric layer with a low dielectric constant and a second dielectric layer with a higher dielectric constant, where the second dielectric layer is removed from the anti-fuse device region, reducing the programming voltage while maintaining a thick dielectric layer for the core device region to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick dielectric layer is used in the anti-fuse device structure, then the reliability of the core device structure is improved, but the programming voltage of the anti-fuse device structure becomes high
Solution Approach 1:
The dielectric layer is segmented into two distinct layers: a first dielectric layer with lower dielectric constant and a second dielectric layer with higher dielectric constant. This segmentation allows different regions of the semiconductor structure to have optimized dielectric properties - the thicker second dielectric layer provides reliability for core devices while the thinner first dielectric layer enables lower programming voltage for anti-fuse devices.
Solution Approach 2:
Different regions of the semiconductor structure are assigned different dielectric layer configurations. The core device region receives both dielectric layers with the second layer providing enhanced reliability, while the anti-fuse device region retains only the first dielectric layer to achieve lower programming voltage. This local quality differentiation resolves the contradiction between global reliability requirements and local programming voltage requirements.
2Reliability
If a single thick dielectric layer is used for both core device and anti-fuse device regions, then the core device reliability is enhanced, but the anti-fuse device programming voltage increases
Solution Approach 1:
The unified dielectric layer is segmented into two functional layers with different dielectric constants. The second dielectric layer with higher dielectric constant is positioned to primarily benefit core device reliability, while the first dielectric layer with lower dielectric constant facilitates easier programming operation of anti-fuse devices by reducing the required programming voltage.
Solution Approach 2:
The dielectric structure is configured with local quality variations where the core device region benefits from the high dielectric constant second layer for reliability, while the anti-fuse device region operates with the lower dielectric constant first layer for ease of programming. This resolves the contradiction between enhanced reliability and ease of operation by optimizing each region's dielectric properties.
Data Source
AI summary
A semiconductor structure includes: a core device region and an anti-fuse device region, disposed on a same substrate; a first dielectric layer, disposed on the substrate of the core device region and the anti-fuse device region, wherein the first dielectric layer has a first dielectric constant; a second dielectric layer, disposed on the first dielectric layer of the core device region; and a conductive layer, disposed on the second dielectric layer of the core device region and the first dielectric layer of the anti-fuse device region; wherein the second dielectric layer has a dielectric constant larger than the first dielectric constant.