Non-volatile Anti-fuse Rupture Control via Doped Poly-silicon Gate
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Solution Overview
Problem
In programmable non-volatile anti-fuse memory cells, the programming process can result in unintended ruptures that lead to short circuits between word lines and bit lines, causing cell failure and increased power consumption, as the rupture location is not reliably controlled to form a low resistance gate-to-drain diode connection.
Innovation Solution
The memory cells employ a poly-silicon gate with different doping concentrations, where the portion closer to the source is lightly doped and the other portion is more heavily doped, ensuring that the rupture occurs in the heavily doped area, thereby minimizing the risk of short circuits and ensuring a low resistance gate-to-drain diode connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thin gate oxide is ruptured by applying high voltage to program an anti-fuse, then a conductive path is formed, but the rupture may occur at an uncontrolled location causing short circuits or high resistance connections
Solution Approach 1:
The gate is divided into two regions with different oxide thicknesses: a first region with thinner oxide and a second region with thicker oxide. By controlling the rupture to occur in the thinner oxide region, the invention achieves reliable programming while preventing uncontrolled rupture locations that would cause short circuits or high resistance connections.
Solution Approach 2:
The gate oxide is segmented into distinct thickness regions (thinner and thicker portions) to provide controlled rupture characteristics. This segmentation ensures that the rupture occurs in a specific, predictable location rather than at an uncontrolled position, resolving the contradiction between reliability and precision.
2Reliability
If the rupture occurs in an uncontrolled location on the thin gate oxide, then programming may fail, but applying higher voltage to ensure rupture increases the risk of short circuits
Solution Approach 1:
The gate structure incorporates a localized thinner oxide region that serves as a predetermined rupture site. This local quality variation ensures that the rupture occurs reliably in the intended location without requiring excessive voltage that would increase short circuit risk to other parts of the gate.
Solution Approach 2:
The invention converts the potential harm of uncontrolled rupture into a benefit by deliberately creating a thinner oxide region that is designed to rupture. This controlled weakness becomes the desired rupture location, ensuring programming success while preventing harmful short circuits in other areas.
3Reliability
If the rupture creates a highly resistive gate-to-drain diode connection, then the anti-fuse fails to function properly, but controlling the rupture location precisely increases process complexity
Solution Approach 1:
The gate structure uses a localized thinner oxide region to ensure rupture occurs at a specific location that guarantees proper gate-to-drain diode connection. This approach achieves reliable anti-fuse functionality without requiring complex control mechanisms, as the structural design itself guides the rupture to the correct position.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the likelihood of cell failure by ensuring that the rupture occurs in a controlled manner, maintaining the integrity of the memory cell and optimizing power usage by forming a functional n-channel diode-connected transistor.
Implementation Method 1
The poly-silicon gate has a first portion that is more heavily doped than a second portion of the gate
Implementation Method 2
the rupture occurs in the heavily doped area, thereby minimizing the risk of short circuits and ensuring a low resistance gate-to-drain diode connection
Data Source
AI summary
In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.