Dielectric Fin Anti-Fuse Memory Cells for Lower-Voltage PUF States
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Solution Overview
Problem
Existing anti-fuse memory cells in integrated circuits are inefficient in terms of power consumption and integration density due to their design, which makes them challenging to integrate into advanced technologies and vulnerable to tampering.
Innovation Solution
The proposed solution involves anti-fuse memory cells with a symmetrical configuration of reading transistors and programming transistors, where the gate structures of the programming transistors are isolated by a dielectric fin structure, allowing for random breakdown and generation of a unique Physically Unclonable Function (PUF) signature, improving read margin and reducing programming voltage, thus enhancing power efficiency and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional anti-fuse memory cell design is used, then the memory cell can be fabricated with standard processes, but the integration density is low and power consumption is high
Solution Approach 1:
The patent introduces a three-dimensional FinFET structure instead of traditional planar transistors. The FinFET channel is formed as a vertical fin structure extending from the substrate, allowing the gate to wrap around three sides of the channel. This vertical dimensionality increase improves integration density while the gate-all-around configuration enhances control efficiency, reducing leakage current and power consumption.
Solution Approach 2:
The gate structure is nested around the FinFET channel in a gate-all-around configuration, where the gate electrode completely surrounds the channel region. This nested arrangement maximizes the gate's control over the channel, improving device performance and reducing the area required per transistor, thereby increasing integration density while maintaining low power operation.
2Reliability
If gate dielectric breakdown is used for programming, then non-volatile memory state is achieved, but the programming voltage requirement is high causing power inefficiency
Solution Approach 1:
The patent utilizes controlled dielectric breakdown of the gate oxide layer through application of high voltage to create conductive paths. By carefully controlling the breakdown process and subsequent read operations at lower voltages, the system achieves non-volatile memory states with improved power efficiency. The FinFET structure also enables better voltage control due to its enhanced gate-channel coupling.
3Adaptability or versatility
If symmetric configuration of reading and programming transistors is used, then PUF signature generation is enabled, but the device complexity increases
Solution Approach 1:
The symmetric FinFET configuration serves multiple functions: it enables PUF signature generation through random variations in identical structures, maintains standard anti-fuse memory operation, and provides robust authentication capabilities. The same symmetric transistor pair structure is used for both reading and programming operations, reducing design complexity while achieving multi-functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the read margin and power efficiency of the memory cells, enabling the generation of a unique PUF signature, which enhances authentication and reduces the risk of unauthorized access, while allowing for higher integration density and lower power consumption.
Implementation Method 1
A gate dielectric of the programming MOS transistor may be broken down to cause the gate and the source or drain of the programming MOS transistor to be interconnected
Data Source
AI summary
A device includes a memory cell that randomly presents either a first logic state or a second logic state. The memory cell includes: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.