Anti-Fuse GaN Transistor Structure for High-Temperature Stability
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving stable electric characteristics and reliability, particularly in high voltage and high current applications, with materials like silicon exhibiting unstable characteristics at high temperatures and GaN devices being costly.
Innovation Solution
The semiconductor device incorporates a main transistor with a main channel layer and an anti-fuse structure, utilizing materials such as GaN and AlGaN, which includes a sub-channel layer with a 2-dimensional electron gas and a sub-barrier layer, to enhance electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon wafers are used for semiconductor devices, then manufacturing cost is reduced, but electric characteristics become unstable at high temperatures
Solution Approach 1:
The patent employs a composite material structure with a silicon substrate and a silicon carbide (SiC) epitaxial layer. The silicon substrate provides cost-effective manufacturing and mechanical strength, while the SiC layer delivers stable electric characteristics at high temperatures. This composite approach allows the device to leverage the advantages of both materials, resolving the contradiction between manufacturing cost and high-temperature reliability.
2Reliability
If GaN materials are used for semiconductor devices, then high-speed performance and efficiency are improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent applies local quality by using SiC epitaxial layers only in specific regions where high-voltage and high-temperature stability is required, such as the drift region and barrier layer. The bulk substrate remains silicon, maintaining cost-effectiveness. This localized application of premium materials optimizes performance-critical areas without incurring the full cost of a complete GaN or SiC device.
3Reliability
If anti-fuse structure is added to the semiconductor device, then reliability and electric characteristics are improved, but device complexity increases
Solution Approach 1:
The patent merges the anti-fuse structure with the existing transistor architecture by integrating the insulating film layer into the gate stack. The anti-fuse element is formed using the same epitaxial growth and processing steps as the main device structures, combining multiple functions into unified process flows. This integration reduces the need for separate fabrication steps and minimizes the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design improves the electric characteristics and reliability of semiconductor devices, enabling stable operation under high voltage and current conditions while minimizing power loss and maintaining efficiency.
Implementation Method 1
a sub-channel layer including a sub-drift area with a 2-dimensional electron gas, a sub-barrier layer above the sub-channel layer, the sub-barrier layer including a material having an energy band gap different from that of the sub-channel layer
Data Source
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AI summary
A semiconductor device includes a main transistor and an anti-fuse connected to one terminal of the main transistor, wherein the main transistor includes a main channel layer, a main gate electrode above the main channel layer, and a main source electrode and a main drain electrode on both sides of the main gate electrode and connected to the main channel layer, the anti-fuse includes a sub-channel layer, a sub-barrier layer above the sub-channel layer and including a material having a different energy band gap than the sub-channel layer, a sub-gate electrode above the sub-channel layer, a gate semiconductor pattern between the sub-channel layer and the sub-gate electrode, and a sub-source electrode above the sub-channel layer and on one side of the sub-gate electrode, and the main source electrode and the sub-gate electrode, or the main source electrode and the sub-source electrode are electrically connected to each other.