Antifuse Gate Structure Across Isolation Interface
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in replacing defective memory cells after packaging, as fuse operations are ineffective post-packaging, and antifuse methods suffer from reliability issues due to reoxidation and increased area requirements, impacting productivity and yield.
Innovation Solution
An antifuse unit in a semiconductor device is designed with a gate structure extending across the interface between the device isolation layer and the active region, surrounded by a contact, and featuring a stacked structure of gate oxide, polysilicon, metal, and hard mask layers, with specific interlayer insulating layers to enhance etch selectivity and reliability, allowing for controlled rupture of the gate oxide layer under applied voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate size is increased to improve reliability and stability of the antifuse, then the antifuse area is increased, but productivity of the net die is reduced
Solution Approach 1:
The gate structure is positioned to extend across the interface between the device isolation layer and the active region, creating a localized high-reliability antifuse structure at the critical interface area rather than requiring a uniformly large gate area throughout the device
Solution Approach 2:
The gate structure utilizes the vertical dimension by extending across the interface between different layers (device isolation layer and active region), thereby achieving enhanced reliability through three-dimensional positioning rather than simply increasing horizontal gate area
2Ease of repair
If conventional antifuse programming is used, then defective cells can be replaced after packaging, but the gate insulating layer reoxidation in subsequent thermal processes reduces reliability
Solution Approach 1:
The gate structure is designed with extended regions at the interface areas before the actual programming operation, creating a structural configuration that is inherently more resistant to reoxidation during subsequent thermal processes
Solution Approach 2:
The extended gate structure at the interface serves as a protective cushion against reoxidation effects, providing a buffer zone that protects the critical programming interface from thermal damage during subsequent manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability and productivity of the antifuse operation by concentrating rupture energy and increasing the exposed gate area, thereby enhancing the semiconductor device's functionality and reducing defects.
Implementation Method 1
The programming operation of the antifuse device includes breaking down the dielectric between the two conductors by applying a high voltage through antifuse terminals for a sufficient period of time
Data Source
AI summary
An antifuse of a semiconductor device includes a semiconductor substrate including a device isolation layer and an active region, a gate structure extending across an interface between the device isolation layer and the active region, a contact coupled to at least a portion of a sidewall of the gate structure, and a metal interconnection provided on the contact and gate structure.