Anti-fuse Structure With Laser-Etched Defect-Responsive Openings
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Solution Overview
Problem
Existing methods for integrating anti-fuse structures into semiconductor circuits face challenges in efficiently creating conductive paths and repairing defects, as they often require standardized and uniform anti-fuse openings, limiting flexibility and efficiency in addressing circuit defects.
Innovation Solution
A method involving an insulating layer with embedded conductors, where laser etching and lithographic processes are used to form anti-fuse openings, followed by the formation of an under bump metallurgy layer to electrically connect exposed conductors, allowing for customizable and flexible programming of anti-fuse structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standardized anti-fuse openings are used for all chips, then mass production efficiency is improved, but flexibility in addressing specific circuit defects is reduced
Solution Approach 1:
The patent implements a dynamic anti-fuse opening formation process where the decision to form an opening at a specific location is made based on detected circuit defects. The system transitions from a static, pre-determined opening pattern to a dynamic, defect-responsive pattern, allowing openings to be created only where needed while maintaining mass production efficiency through automated defect detection and selective opening formation.
2Adaptability or versatility
If anti-fuse openings are formed for all possible defect locations, then adaptability to any defect is improved, but energy consumption and manufacturing complexity increase
Solution Approach 1:
The patent applies local quality by forming anti-fuse openings only at specific locations where defects are detected, rather than creating openings across the entire chip. This localized approach ensures that energy and manufacturing resources are concentrated only where needed, reducing overall energy consumption and manufacturing complexity while maintaining the ability to address any detected defect.
Solution Approach 2:
The patent implements partial action by creating anti-fuse openings only for the specific defect locations that require repair, rather than forming openings for all possible defect locations. This selective approach avoids excessive manufacturing actions and energy consumption while still providing adequate adaptability to address the actual defects present in each chip.
3Manufacturing precision
If laser etching is used to create anti-fuse openings, then precision in opening formation is improved, but manufacturing complexity and equipment requirements increase
Solution Approach 1:
The patent merges the defect detection process with the anti-fuse opening formation process, integrating these two functions into a coordinated manufacturing workflow. By combining automated optical inspection or electrical testing with subsequent laser processing, the system achieves precise opening formation at defect locations without requiring separate, complex manufacturing stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of anti-fuse structures that can be programmed at different positions on each chip based on specific defects, reducing unnecessary openings and energy consumption, while allowing for mass production with standardized codes.
Implementation Method 1
the insulating layer is etched by a laser to form an anti-fuse opening in the insulating layer
Data Source
AI summary
A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically.