Anti-fuse Circuit Parallel Writing via Latch Storage
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Solution Overview
Problem
The existing anti-fuse circuit technology for semiconductor devices is slow in writing defective addresses due to the need for individual writing on each chip and the long time required for dielectric breakdown, which can result in unsuccessful writing and the need to abandon entire chips.
Innovation Solution
Incorporating a latch circuit to temporarily store data to be written to the anti-fuse element, allowing for high-speed writing in parallel across multiple chips, along with a control circuit to manage the write and read transistors, and a disable circuit to invalidate fuse sets for unsuccessful writes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If writing is performed directly to anti-fuse elements using dielectric breakdown, then nonvolatile storage is achieved, but writing time becomes extremely long (5 seconds per chip for 1000 fuse sets)
Solution Approach 1:
The patent introduces a latch circuit that temporarily stores defective address data before writing to the anti-fuse element. This preliminary action allows the system to prepare data in high-speed latch circuits first, then transfer to anti-fuse elements in batches, significantly reducing the overall writing time while maintaining nonvolatile storage reliability.
2Reliability
If individual writing is performed on each chip, then correct defective address storage is achieved, but writing operation cannot be performed in parallel across multiple chips
Solution Approach 1:
The patent segments the writing operation into two distinct phases: first, parallel data loading into latch circuits across multiple chips; second, sequential transfer to anti-fuse elements. This segmentation allows different chips to be processed in parallel during the loading phase, improving productivity while ensuring accuracy through individualized address storage in the latch circuits before final commitment to anti-fuse elements.
3Reliability
If high voltage is applied to cause dielectric breakdown for writing, then information is stored in anti-fuse element, but resistance after breakdown deviates greatly making it difficult to determine successful writing
Solution Approach 1:
The patent introduces a sense amplifier as an intermediary component between the anti-fuse element and the measurement system. The sense amplifier detects and amplifies the resistance change caused by dielectric breakdown, converting the difficult-to-measure megaohm-level resistance into a detectable signal, thereby enabling precise determination of writing success while maintaining reliable information storage.
4Reliability
If writing time for one fuse set is 5 milliseconds, then dielectric breakdown is achieved, but total writing time for 1000 fuse sets becomes about 5 seconds per chip
Solution Approach 1:
The patent implements preliminary action by loading data into latch circuits before transferring to anti-fuse elements. This allows multiple chips to be prepared in parallel during the latch loading phase, then transferred to anti-fuse elements in an optimized sequence, reducing the total writing time from 5 seconds per chip to a much faster process while maintaining the reliability of dielectric breakdown writing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed writing of defective addresses to anti-fuse elements, reducing the time required for the process and preventing the need to abandon entire chips by allowing parallel writing and invalidating individual fuse sets.
Implementation Method 1
Writing of the information to the anti-fuse element is performed by dielectric breakdown caused by applying a high voltage
Data Source
AI summary
An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus, even when the defective addresses respectively different are written in a plurality of chips, a writing process to the latch circuit can be completed in a very short period of time. Thereby, an actual process for writing to the anti-fuse element can be performed in parallel for the chips, and as a result, the process for writing to the anti-fuse element can be performed at high speed.