Anti-Fuse IC Layout With Parallel Via Paths for Lower Resistance
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Solution Overview
Problem
Integrated circuits (ICs) with anti-fuse bits face limitations in programming and read operations due to high path resistance, which can be attributed to the fewer electrical connections between active areas, leading to reduced current flow and performance.
Innovation Solution
Increasing the number of electrical connections between active areas to anti-fuse bits from four to enhance current paths, thereby reducing path resistance and improving both programming and read operations by configuring anti-fuse layouts with additional conductive regions and via regions to facilitate more parallel current paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of electrical connections between active areas to anti-fuse bits is increased, then path resistance decreases and current flow improves, but device complexity increases due to additional conductive regions and via regions
Solution Approach 1:
The patent divides the electrical connection path into multiple parallel segments by adding additional conductive regions and via regions. Instead of a single connection path, multiple segmented paths are created between active areas and anti-fuse bits, allowing current to flow through parallel routes which reduces overall path resistance while distributing the complexity across manageable layout segments.
Solution Approach 2:
The patent utilizes vertical dimension by adding multiple via regions that connect different metal layers. Instead of only horizontal routing in a single plane, the solution extends connections into the vertical dimension with vias penetrating through dielectric layers, creating three-dimensional connection paths that reduce resistance without significantly increasing lateral layout complexity.
2Productivity
If additional conductive regions and via regions are added to create parallel current paths, then path resistance reduces and current flow increases, but manufacturing complexity increases
Solution Approach 1:
The additional conductive regions and via regions serve multiple functions simultaneously: they provide parallel current paths for reduced resistance, act as routing channels for signal distribution, and offer redundant connection paths for defect tolerance. This multi-functionality justifies the increased manufacturing complexity by delivering multiple benefits from the same structural additions.
Solution Approach 2:
The patent modifies the electrical parameters of the connection paths by changing the number of parallel paths and the dimensions of conductive regions. By adjusting parameters such as via diameter, conductive region width, and path length, the solution optimizes current flow efficiency while managing manufacturing complexity through controlled parameter variations rather than fundamental design changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased number of electrical connections reduces path resistance, enhancing current flow and improving the performance of anti-fuse bit programming and read operations, leading to more efficient IC device manufacturing.
Implementation Method 1
a programming electric field is applied across the dielectric material layer to sustainably alter (e.g., break down) the dielectric material, thus decreasing the resistance of the dielectric material layer
Data Source
AI summary
A method of generating an IC layout diagram includes abutting first and second cells to define a first active region including first and second anti-fuse bits, abutting third and fourth cells to define a second active region including third and fourth anti-fuse bits, and defining a third active region including fifth and sixth anti-fuse bits adjacent to the first through fourth anti-fuse bits. The first cell includes first and second via regions overlapping first and second gate regions shared by respective structures and transistors of the first, third, and fifth anti-fuse bits, the fourth cell includes third and fourth via regions overlapping third and fourth gate regions shared by respective transistors and structures of the second, fourth, and sixth anti-fuse bits, the third cell includes fifth and sixth via regions overlapping the first gate region, and the second cell includes seventh and eighth via regions overlapping the fourth gate region.