Antifuse Memory Array Using SOI and Crosspoint Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional one-time programmable (OTP) memory technologies, such as antifuse memories, face challenges in reducing area per bit and are costly due to complex manufacturing processes, particularly the use of trench structures, which hinder the development of more compact and cost-effective memory solutions.
Innovation Solution
The implementation of a semiconductor-on-insulator (SOI) wafer with a buried oxide layer, isolation regions, and a compact antifuse dielectric structure, where bit lines and word lines are formed using conductivity implants and patterned conductive layers, allowing for efficient electrical programming and read operations without the need for deep trenches, enabling a compact and cost-effective OTP memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitor structures with select transistors and isolation elements are used to implement antifuse memory, then reliable information storage is achieved, but area per bit increases reducing memory density
Solution Approach 1:
The patent extracts and eliminates the select transistor and isolation elements from the traditional antifuse memory cell structure. By using a crosspoint array architecture where word lines and bit lines directly intersect at the antifuse location, the patent removes the need for additional selecting components, thereby reducing area per bit while maintaining reliable information storage through the inherent selectivity of the crosspoint configuration
Solution Approach 2:
The patent merges the functions of selection and storage into a single integrated structure. The crosspoint array combines word lines, bit lines, and antifuses into a unified architecture where the intersection point itself performs both addressing and storage functions, eliminating the need for separate select transistors and isolation elements
2Area of moving object
If crosspoint array architecture is used to reduce cell size, then area per bit is reduced, but manufacturing complexity increases due to deep trench requirements
Solution Approach 1:
The patent changes the structural parameters of the crosspoint array by eliminating deep trench requirements. Instead of fabricating antifuses in deep isolation trenches, the patent uses a planar or shallow structure where antifuses are positioned at the intersection of word and bit lines, significantly simplifying the manufacturing process while maintaining reduced cell size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a high-density, compact OTP memory array that is more efficient in area usage and cost-effective, with improved manufacturing simplicity, allowing for flexible programming after circuit manufacture and efficient integration into integrated circuits.
Implementation Method 1
a dielectric layer such as an oxide is subjected to a high electric field to generate a tunneling current through the dielectric
Implementation Method 2
The tunneling current leads to a phenomenon known as hard dielectric breakdown
Implementation Method 3
A first conductivity implant is implanted into the semiconductor layer... A second conductivity implant, different from the first conductivity type, is implanted into the semiconductor layer
Data Source
AI summary
A method for making a one time programmable (OTP) memory array includes providing a wafer comprising a buried insulator layer and a semiconductor layer over the buried insulator layer and forming a plurality of bit lines in the semiconductor layer. Each of the plurality of bit lines comprise a portion of the semiconductor layer and the plurality of bit lines are separated from each other by isolation regions formed in the semiconductor layer. The method further includes forming an anti-fuse dielectric layer over and in physical contact with the plurality of bit lines and the isolation regions, and forming a plurality of word lines over and in physical contact with the anti-fuse dielectric layer.