Anti-fuse OTP Memory Cell with Extended Auxiliary Gate
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Solution Overview
Problem
As semiconductor manufacturing processes continue to miniaturize, existing anti-fuse one-time programmable (OTP) memory cells face challenges such as electron or hole leakage in floating-gate OTP memories and limitations with polysilicon gates, which restrict their compatibility with advanced processes.
Innovation Solution
The proposed anti-fuse OTP memory cell features a simpler structure with only one floating gate and one auxiliary gate, where the auxiliary gate is extended to cover part or all of a second active region, optimizing the ratio of floating gate to auxiliary gate area and oxide thickness to facilitate low-voltage breakdown and programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating-gate OTP memory is used, then data can be stored nonvolentially, but electrons or holes are easily leaked in advanced processes causing data loss
Solution Approach 1:
The patent extracts the problematic floating gate structure and replaces it with an anti-fuse structure consisting of a gate oxide layer and a breakage layer. This removes the source of electron or hole leakage while preserving the nonvolatile memory storage capability through physical breakdown of the gate oxide layer.
Solution Approach 2:
The gate oxide layer is designed as a consumable element that undergoes irreversible physical breakdown during programming. Once broken down, it remains in a permanent conductive state, providing reliable nonvolatile storage without the risk of charge leakage that plagues floating-gate structures.
2Reliability
If polysilicon gate is used in electric fuse OTP memory, then low-resistance state can be achieved, but usage is restricted when replaced with metal gate in advanced processes
Solution Approach 1:
The anti-fuse structure with gate oxide layer and breakage layer is designed to be process-agnostic, working equally well with polysilicon gates in current processes and metal gates in advanced processes. This universal design eliminates the restriction of process compatibility while maintaining memory state stability through the physical breakdown mechanism.
3Adaptability or versatility
If conventional anti-fuse OTP memory cell structure is used, then high compatibility with advanced processes is achieved, but device size can be further reduced
Solution Approach 1:
The patent merges the gate structure of the first MOS transistor with the gate structure of the second MOS transistor by extending the gate electrode and gate oxide layer continuously across both active regions. This shared gate structure reduces the total number of gate components and minimizes the overall memory cell area while maintaining process compatibility.
Solution Approach 2:
The gate electrode and gate oxide layer are extended in the second direction perpendicular to the first direction, passing through the isolation region to cover part or all of the second active region. This dimensional extension allows a single gate structure to control multiple transistors, reducing device footprint.
4Ease of operation
If auxiliary gate oxide thickness is reduced, then breakdown voltage is lowered for easier programming, but breakdown position control becomes more challenging
Solution Approach 1:
The breakage layer is introduced as a localized thin layer with different material composition and thickness compared to the gate oxide layer. This local quality change creates a preferred breakdown path at specific locations within the gate stack, enabling controlled breakdown position even when the gate oxide layer is thin, thus facilitating low-voltage programming while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a smaller size, better performance, and reduced breakdown voltage requirements, while ensuring that the breakdown positions of the auxiliary gate oxide layers are more concentrated and consistent across multiple memory cells.
Implementation Method 1
The anti-fuse OTP memory is based on the mechanism of physical breakdown of the gate oxide layer
Data Source
AI summary
A one-time programmable nonvolatile memory cell includes a substrate providing a first conductivity type well and a second conductivity type well, a first MOS transistor having a floating gate and a gate oxide, and an auxiliary gate and a gate oxide formed by extending one end of the floating gate and the gate oxide of the first MOS transistor from an edge of the first active region, along a second direction perpendicular to the first direction, passing through the isolation region until to cover a part or an entire of the second active region. The first and the second active regions are separated by an isolation region, and the first and second active regions and the isolation region are arranged parallel to each other along a first direction. The memory cell has an improved structure and optimized performance and a reduced size.