Anti-Fuse Memory Cell Layout for Faster Gate Dielectric Breakdown
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Solution Overview
Problem
In nanosheet transistor configurations for anti-fuse memory cells, the presence of inner spacers between gate stacks and source/drain features increases the time and voltage required to break down the gate dielectric, thereby affecting the overall performance of the memory cell.
Innovation Solution
The memory cell is configured with a programming transistor having reduced dielectric materials between gate stacks and source/drain features, while the reading transistor has increased dielectric materials, allowing the programming transistor to be in direct contact with its source/drain features and the reading transistor to have inner spacers for electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inner spacers are present between gate stacks and source/drain features in programming transistor, then parasitic capacitance is suppressed, but breakdown voltage and time increase
Solution Approach 1:
The patent applies different structural configurations to different transistors within the same memory cell. The programming transistor is configured without inner spacers to enable faster breakdown, while the reading transistor includes inner spacers for parasitic capacitance suppression. This local differentiation resolves the contradiction by optimizing each transistor's structure according to its specific functional requirements rather than applying a uniform design
2Reliability
If inner spacers are present between gate stacks and source/drain features, then parasitic capacitance is suppressed, but programming speed decreases
Solution Approach 1:
The invention implements local quality differentiation by configuring the programming transistor without inner spacers to maximize programming speed, while the reading transistor includes inner spacers for parasitic capacitance suppression. This resolves the speed-reliability contradiction by applying the appropriate structural optimization to each transistor type based on its operational priorities
3Loss of time
If dielectric materials are reduced between gate stacks and source/drain features, then breakdown voltage and time are reduced, but parasitic capacitance increases
Solution Approach 1:
The patent segments the memory cell into two distinct transistor configurations: the programming transistor with minimal dielectric materials for fast breakdown, and the reading transistor with inner spacers for parasitic capacitance control. This segmentation allows each transistor to be optimized independently, resolving the contradiction between breakdown speed and parasitic capacitance management
Solution Approach 2:
Different dielectric material configurations are applied locally to different transistors based on their functional requirements. The programming transistor uses reduced dielectric materials for speed optimization, while the reading transistor uses increased dielectric materials with inner spacers for parasitic capacitance suppression, thereby resolving the harmful effect locally where it occurs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the breakdown voltage and time for the programming transistor, while maintaining effective parasitic capacitance suppression in the reading transistor, thereby enhancing the operational speed and programming yield of the anti-fuse memory cell.
Implementation Method 1
A gate dielectric of the programming MOS transistor may be broken down to cause the gate and the source or drain region of the programming MOS transistor to be interconnected
Data Source
AI summary
A memory device includes first nanostructures stacked on top of one another; first gate stacks, where two adjacent ones of the first gate stacks wrap around a corresponding first nanostructure; second nanostructures stacked on top of one another; second gate stacks, where two adjacent ones of the second gate stacks wrap around a corresponding second nanostructure; a first drain/source feature electrically coupled to a first end of the first nanostructures; a second drain/source feature electrically coupled to both of a second end of the first nanostructures and a first end of the second nanostructures; and a third drain/source feature electrically coupled to a second end of the second nanostructures. At least one of the plurality of first gate stacks is in direct contact with at least one of the first drain/source feature or the second drain/source feature.