Anti-Fuse Memory Cell Layout for Reading Transistor Breakdown Reliability
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Solution Overview
Problem
Existing anti-fuse memory devices have compromised reading transistor performance due to identical crystal lattice directions in both programming and reading transistors, leading to undesirable shorter breakdown times and reduced reliability.
Innovation Solution
The memory cell configuration includes a fin-based programming transistor and nanosheet reading transistors with different crystal lattice directions, ensuring the programming transistor maintains decent programming performance while improving the reliability of the reading transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If identical crystal lattice directions are used in both programming and reading transistors, then the programming transistor achieves decent programming performance, but the reading transistor suffers from shorter breakdown time and reduced reliability
Solution Approach 1:
The patent applies different crystal lattice directions to different transistor types within the same memory cell. Specifically, the programming transistor uses a first crystal lattice direction optimized for programming performance, while the reading transistor uses a second crystal lattice direction optimized for reliability and extended breakdown time. This local differentiation allows each transistor to be optimized for its specific function without compromising the other.
Solution Approach 2:
The patent segments the crystal lattice orientation parameter across different transistor components. By dividing the memory cell into distinct programming and reading transistor regions with different crystal orientations, the patent enables independent optimization of each segment's properties to meet its specific performance requirements.
2Reliability
If different crystal lattice directions are used in programming and reading transistors, then the reading transistor reliability is improved with extended breakdown time, but the device complexity increases
Solution Approach 1:
The patent changes the crystal lattice direction parameter between programming and reading transistors to achieve different performance characteristics. By systematically varying this fundamental material parameter, the patent optimizes each transistor type for its specific function while maintaining overall device integration.
Data Source
AI summary
A method for fabricating a semiconductor device includes: forming a fin-based structure protruding from a top boundary of a substrate; forming a first nanosheet-based structure protruding from the top boundary of the substrate; epitaxially growing a first, a second, and a third source/drain (S/D) regions, the first S/D region disposed between the fin-based structure and the first nanosheet-based structure, the second S/D region disposed opposite the fin-based structure from the first S/D region, and the third S/D region disposed opposite the first nanosheet-based structure from the first S/D region, and the first to the third S/D regions having a same conductive type; forming a second nanosheet-based structure protruding from the boundary of the substrate and laterally spaced apart from the first nanosheet-based structure; and epitaxially growing a fourth S/D region disposed opposite the second nanosheet-based structure from the third S/D region.