Anti-fuse Memory Cell Circuit with Positive Feedback Loops
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Solution Overview
Problem
Current one-time programmable memory devices face issues with high static power consumption, poor reliability of readout circuits, complex control circuits, and inflexible layout.
Innovation Solution
The anti-fuse memory cell circuit design includes a pure combinational circuit with switch and logic operation modules forming positive feedback loops, reducing static power consumption to near zero and enhancing readout reliability, while simplifying timing control and allowing flexible layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If traditional one-time programmable memory readout circuits are used, then data can be read from memory cells, but the circuit exhibits high static power consumption
Solution Approach 1:
The readout circuit uses periodic clock signals to control the operation of flip-flops and multiplexers, enabling the circuit to operate only when needed rather than continuously. This periodic operation significantly reduces static power consumption while maintaining reliable data reading functionality through synchronized state transitions.
Solution Approach 2:
The circuit incorporates feedback mechanisms through cross-coupled flip-flops that maintain their state until a read operation is initiated. The feedback loops ensure stable state retention without continuous power consumption, while enabling reliable data output when clocked appropriately.
2Reliability
If complex control circuits are used to manage memory operations, then reliable read/write operations can be achieved, but the control circuit complexity increases
Solution Approach 1:
The circuit combines multiple control functions into integrated blocks such as unified control logic that manages both row and column selections, and combined read/write control that handles both operations through shared circuitry. This merging reduces the overall number of separate control circuits while maintaining operational reliability through coordinated control signals.
Solution Approach 2:
The control circuit is designed with universal components that can perform multiple functions. For example, the same control logic and signal lines are used for both read and write operations, and the same circuit blocks handle different memory cell selections. This multi-functionality reduces control circuit complexity while ensuring reliable operation across different memory access modes.
3Manufacturing precision
If fixed memory cell layout is used, then manufacturing precision can be maintained, but layout flexibility is reduced
Solution Approach 1:
The memory array is divided into independently addressable blocks with standardized interfaces. Each memory cell within a block can be independently selected through row and column decoding, allowing the physical layout to be optimized for manufacturing while maintaining flexible logical addressing. This segmentation enables precise manufacturing control at the cell level while providing layout flexibility at the block level.
Solution Approach 2:
The memory organization uses two-dimensional row and column addressing to access memory cells. This dimensional approach allows the physical layout to follow precise manufacturing patterns in both directions while the logical addressing provides flexible access patterns. The decoupling of physical layout constraints from logical access patterns enables both manufacturing precision and layout flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves lower static power consumption, improved readout reliability, simplified control logic, and flexible circuit layout, addressing the limitations of existing one-time programmable memory technologies.
Implementation Method 1
A voltage pulse, which is coupled to the first capacitive plate of the anti-fuse element, has a potential sufficiently high to cause a current to flow through the anti-fuse element that destroys at least a portion of the dielectric layer, thereby electrically shorting the first and second capacitive plates.
Data Source
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AI summary
An anti-fuse storage unit circuit and array circuit and a read/write method therefor. The anti-fuse storage unit circuit comprises: an anti-fuse device; a switch module coupled to the anti-fuse device; a selection module coupled to the switch module; and a control module (12) coupled to the anti-fuse device and the switch module respectively; the control module (12) is used to switch an on-off mode of the switch module according to a breakdown state of the anti-fuse device. The anti-fuse storage unit circuit has advantages that: 1, said storage unit circuit is a pure combinational circuit, and compared with a sequential circuit, after a delay of some time, all paths of said storage unit circuit are turned off and the whole circuit has no logic action, the static power consumption is low, and the power consumption is approximately 0; 2, two positive feedback loops are substantially formed by means of the design of the switch module and a logic operation module, so that a reading circuit can read "0" or "1" more reliably; 3, a complex sequential control portion is omitted, and even outputs OUTA/OUTB of the reading circuit can be not latched and directly used as coding outputs of an anti-fuse; and 4, the layout wiring of the circuit is flexible.