Anti-Fuse Memory Cell Nanostructures for Programming and Read Accuracy
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Solution Overview
Problem
Existing anti-fuse memory cells face challenges in programming yield and reading accuracy due to the size of the gate dielectric, which affects the conductivity and differentiation of current levels during programming and reading operations.
Innovation Solution
The memory cells are configured with a programming transistor having narrower nanostructure channels and reading transistors with wider nanostructure channels, enhancing the programming yield and reading accuracy by optimizing the gate dielectric area and current magnitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the gate dielectric area is increased to improve reading accuracy, then the current conducting capability is enhanced, but the programming yield deteriorates due to reduced breakdown probability
Solution Approach 1:
The patent divides the memory cells into two distinct groups: anti-fuse memory cells with larger gate dielectric area for high reading accuracy, and fuse memory cells with smaller gate dielectric area for high programming yield. This segmentation allows each group to be optimized for its specific function without compromise.
Solution Approach 2:
Different regions of the memory array are assigned different gate dielectric area characteristics. The anti-fuse portion uses larger gate dielectric area to enhance current conducting capability and reading accuracy, while the fuse portion uses smaller gate dielectric area to maximize breakdown probability and programming yield. Each local region has quality tailored to its specific operational requirements.
2Reliability
If the gate dielectric area is decreased to improve programming yield, then the breakdown probability increases, but the reading accuracy deteriorates due to reduced current magnitude
Solution Approach 1:
The memory array is segmented into fuse memory cells and anti-fuse memory cells with distinct gate dielectric area characteristics. Fuse cells with smaller gate dielectric area are optimized for programming operations where breakdown probability is critical, while anti-fuse cells with larger gate dielectric area are optimized for reading operations where current magnitude and differentiation are critical.
Solution Approach 2:
The patent implements local quality by assigning different gate dielectric area sizes to different functional regions. The fuse portion uses minimized gate dielectric area to maximize programming reliability through increased breakdown probability, while the anti-fuse portion uses maximized gate dielectric area to enhance reading accuracy through increased current conducting capability.
3Device complexity
If a unified gate dielectric area is used for all memory cells, then the device complexity is reduced, but both programming yield and reading accuracy cannot be simultaneously optimized
Solution Approach 1:
Rather than using a unified gate dielectric area for all cells, the patent segments the memory array into two distinct types of memory cells with different gate dielectric area characteristics. This segmentation enables simultaneous optimization of programming yield and reading accuracy, accepting increased device complexity as necessary for achieving both performance targets.
Solution Approach 2:
The patent rejects the simplified unified approach in favor of local quality differentiation. Each portion of the memory array (fuse and anti-fuse) receives gate dielectric area sizing specifically tailored to its operational requirements, enabling both programming and reading functions to operate at optimal performance levels despite the increased structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves programming yield and reading accuracy by increasing the chance of gate dielectric breakdown and enhancing the current conducting capability, allowing for better differentiation of logic states.
Implementation Method 1
A gate dielectric of the programming MOS transistor may be broken down to cause the gate and the source or drain sub-feature of the programming MOS transistor to be interconnected
Data Source
AI summary
A memory device includes a programming transistor and a reading transistor of an anti-fuse memory cell. The programming transistor includes first semiconductor nanostructures vertically spaced apart from one another, each of the first semiconductor nanostructures having a first width along a first lateral direction. The reading transistor includes second semiconductor nanostructures vertically spaced apart from one another, each of the second semiconductor nanostructures having a second width different from the first width along the second direction. The memory device also includes a first and a second gate metals. The first gate metal wraps around each of the first semiconductor nanostructures with a first gate dielectric disposed therein. The second gate metal wraps around each of the second semiconductor nanostructures with a second gate dielectric disposed therein.