Antifuse Memory Cell Pair Programming for Random Number Generation
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Solution Overview
Problem
Existing random number generator devices and PUF systems lack a simple and efficient method to ensure that only one of each pair of memory cells is programmed, leading to inconsistent identification codes and random number generation.
Innovation Solution
A random number generator device comprising two antifuse one-time programmable memory cells, a bias line, bit lines, a voltage generator, and a control circuit that applies bias and bit line voltages to program the cells simultaneously, stopping programming once one cell is fully programmed due to intrinsic fabrication variations, resulting in distinct statuses for each cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are programmed simultaneously using the same voltage, then programming efficiency is improved, but it becomes difficult to ensure that only one cell is fully programmed
Solution Approach 1:
The patent implements a feedback mechanism by monitoring the programming status of memory cells through sensing circuits. When one cell reaches full programming status, the system detects this state and adjusts the programming voltage accordingly to prevent over-programming and ensure only one cell is fully programmed, thus resolving the contradiction between programming efficiency and control precision
Solution Approach 2:
The patent dynamically changes programming parameters (voltage levels, pulse widths) based on real-time cell status. By adjusting these parameters during the programming process, the system maintains high efficiency while achieving precise control over which single cell becomes fully programmed
2Reliability
If complex control mechanisms are added to ensure single cell programming, then programming reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the control function into the existing memory cell structure by utilizing shared bit lines and word lines for both programming and sensing operations. This integration approach achieves reliable single-cell programming without adding separate complex control circuits, thus maintaining simplicity while improving reliability
3Reliability
If intrinsic fabrication variations are utilized for random number generation, then security is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent deliberately exploits the inherent asymmetry and variations in fabrication processes among different memory cells. Rather than requiring high manufacturing precision, the system uses these natural variations as the basis for generating unique, secure random numbers, thus achieving high security while accepting broader manufacturing tolerances
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that only one memory cell is fully programmed, generating a reliable random number bit based on the different programmed statuses, enhancing the security and efficiency of identification and encoding operations.
Implementation Method 1
Each of the two memory cells is an antifuse one-time programmable memory cell
Implementation Method 2
The voltage generator programs the two memory cells by applying a bias voltage to the bias line and applying a bit line voltage to the first bit line and the second bit line
Data Source
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AI summary
A random number generator device (100, 200, 600, 900, 1200) has at least at least a memory unit (110, 210, 610, 910, 1210), a voltage generator (130), and a control circuit (140). Each memory unit (110, 210, 610, 910, 1210) has two memory cells (120A, 120B, 220A, 220B, 620A, 620B, 920A, 920B, 1220A, 1220B), one of the two memory cells (120A, 120B, 220A, 220B, 620A, 620B, 920A, 920B, 1220A, 1220B) is coupled to a bias line (CL, WL, PL, SL) and a first bit line (BL1), and another of the two memory cells (120A, 120B, 220A, 220B, 620A, 620B, 920A, 920B, 1220A, 1220B) is coupled to the bias line (CL, WL, PL, SL) and a second bit line (BL2). The voltage generator provides the two memory cells (120A, 120B, 220A, 220B, 620A, 620B, 920A, 920B, 1220A, 1220B) a bias voltage (Va), a first bit line voltage (V1) and a second bit line voltage (V2) via the bias line (CL, WL, PL, SL), the first bit line (BL1) and the second bit line (B12) respectively. The control circuit (140) shorts the first bit line (BL1) and the second bit line (BL2) to program the two memory cells (120A, 120B, 220A, 220B, 620A, 620B, 920A, 920B, 1220A, 1220B) simultaneously during a programming period (Dp) and generates a random number bit (N1) according the statuses of the two memory cells (120A, 120B, 220A, 220B, 620A, 620B, 920A, 920B, 1220A, 1220B) during a reading period (Dr).