Antifuse Memory Cell for Physically Unclonable Function Security
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Solution Overview
Problem
Existing physically unclonable function (PUF) technologies face challenges in generating unique random codes for semiconductor chips due to limitations in one-time programming memory cells, particularly in isolating complementary antifuses, which affects security and data protection applications.
Innovation Solution
The design of a one-time programming memory cell and memory array using antifuse transistors with differential gate oxide layers, where the thinner part of the gate oxide layer is more susceptible to rupture, allowing for the generation of random codes through controlled voltage applications during programming and reading cycles, enabling secure unique code generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two complementary antifuses are directly connected in a one-time-programmable memory cell, then the device structure is simple, but it is impossible to isolate the two complementary antifuses which compromises security
Solution Approach 1:
The memory cell is divided into two independent antifuse transistors (first antifuse transistor and second antifuse transistor) with separate gate terminals. Each antifuse transistor can be independently controlled through its own gate terminal, enabling selective programming and reading operations while maintaining physical isolation between the complementary antifuses.
Solution Approach 2:
A control transistor is introduced as an intermediary element between the two complementary antifuses. This control transistor enables selective connection or isolation of the antifuses based on programming requirements, providing the necessary isolation capability while maintaining a relatively simple overall structure.
2Adaptability or versatility
If a one-time-programmable memory cell uses two complementary antifuses, then random code generation capability is achieved, but the inability to isolate them affects security for data protection applications
Solution Approach 1:
The memory cell structure is segmented into independently controllable antifuse transistors with separate gate terminals, allowing selective activation and isolation of complementary antifuses to enhance security while maintaining random code generation capability.
Solution Approach 2:
The memory cell is designed with preliminary isolation mechanisms through separate gate terminals and control transistors, enabling security-critical isolation operations to be performed before data protection requirements are fully implemented, ensuring secure random code generation from the outset.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively generates unique random codes for PUF technology by utilizing the manufacturing variation of the gate oxide layers, ensuring secure data protection and high security requirements are met, as the ruptured states of the antifuse transistors provide distinct resistance values for coding.
Implementation Method 1
the gate terminal (315) of the first antifuse transistor (A1) comprises a first gate oxide layer (352) with a first part and a second part, and the first part (352a) is thinner than the second part
Implementation Method 2
a first antifuse transistor (A1), wherein a first drain/source terminal of the first antifuse transistor (A1) is connected with the first bit line (BL)
Data Source
Figure 1A~1B
Figure 2A~3A
Figure 3B~3C
AI summary
An one time programming memory cell is provided. A first drain/source terminal of the first antifuse transistor is connected with a bit line, and a gate terminal of the first antifuse transistor is connected with a first antifuse control line. The first antifuse transistor comprises a gate oxide layer with a first part and a second part, and the first part is thinner than the second part. A first drain/source terminal of the second antifuse transistor is connected with a second drain/source terminal of the first antifuse transistor, a gate terminal of the second antifuse transistor is connected with a second antifuse control line, and a second drain/source terminal of the second antifuse transistor is connected with the bit line. The second antifuse transistor comprises a second gate oxide layer with a third part and a fourth part, and the third part is thinner than the fourth part.