Anti-fuse Memory Cell Segmented Gate Oxide for Current Flow
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Solution Overview
Problem
Existing anti-fuse memory cells face issues with low current flow and high current variation due to weak inversion in the channel region, especially when using high-k metal gates, where the read voltage must be kept low to prevent breakdown of the thin gate oxide layer, leading to inefficient programming and reading operations.
Innovation Solution
The proposed anti-fuse memory cell design includes a program gate oxide layer configured to break down independently between the program gate and channel regions, allowing for conduction upon a program voltage difference, with select gates and a high-k program gate oxide layer, enabling controlled breakdown and improved current flow by applying different voltages to selected and unselected gates during programming and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a low read voltage is applied to prevent breakdown of the thin gate oxide layer, then the integrity of the gate oxide layer is maintained, but weak inversion in the channel region occurs leading to low current flow and high current variation
Solution Approach 1:
The gate oxide layer is segmented into two distinct regions: a first gate oxide layer with a first thickness and a second gate oxide layer with a second thickness greater than the first thickness. This segmentation allows different voltage thresholds for breakdown in different regions, enabling the read operation to use a higher voltage that strongly inverts the channel without causing unwanted breakdown, thereby increasing current flow while maintaining reliability.
Solution Approach 2:
Different regions of the gate oxide layer are given different local properties (thicknesses) to serve different functions. The thinner first gate oxide layer enables breakdown for programming, while the thicker second gate oxide layer prevents breakdown during reading. This local quality differentiation resolves the contradiction between needing high voltage for strong inversion and avoiding breakdown.
2Adaptability or versatility
If a high-k metal gate oxide layer is used to scale voltage, then voltage scaling is achieved, but the read voltage must be kept low to prevent breakdown, causing weak inversion and high current variation
Solution Approach 1:
The gate oxide layer is divided into segments with different thicknesses, allowing the system to maintain voltage scaling benefits while creating a thicker region that raises the breakdown voltage threshold. This enables use of higher read voltages for strong channel inversion without causing breakdown, reducing current variation.
3Reliability
If the gate oxide layer thickness is increased to prevent breakdown, then breakdown resistance is improved, but the programming efficiency decreases due to reduced field strength
Solution Approach 1:
The gate oxide layer is segmented such that the first region maintains thin thickness for efficient programming (high field strength), while the second region has increased thickness for breakdown resistance. During programming, the thin region enables efficient charge injection, while during reading, the thick region prevents unwanted breakdown.
Solution Approach 2:
Different regions of the gate oxide layer have different local thickness properties optimized for different operations. The thin region provides high field strength for programming efficiency, while the thick region provides breakdown resistance for reliability during reading operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances current flow by approximately 108% and reduces current variation standard deviation by 47%, improving the memory cell's programming efficiency and readability, while maintaining the integrity of the gate oxide layer during read operations.
Implementation Method 1
The program gate oxide layer may be configured to break down to allow conduction between the program gate and at least one of the channel regions upon providing a program voltage difference between the program gate and at least one of the channel regions
Data Source
AI summary
An anti-fuse memory cell may include a substrate including first and second conductivity regions and an isolation region at least partially within the substrate, a program gate over the substrate, a program gate oxide layer over the isolation region and between the program gate and the substrate, a first channel region arranged laterally between the first conductivity region and the isolation region, a second channel region arranged laterally between the second conductivity region and the isolation region, a first select gate arranged over the substrate and over the first channel region and a second select gate arranged over the substrate and over the second channel region. The program gate oxide layer may be configured to break down to allow conduction between the program gate and at least one of the channel regions upon providing a program voltage difference between the program gate and at least one of the channel regions.