Anti-fuse Memory Circuit Voltage Fluctuation Read Error
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Solution Overview
Problem
The internal power voltage fluctuations in devices cause read errors in anti-fuse memory cells, as the reference voltage remains unchanged, leading to incorrect interpretation of data levels when the voltage is high or low.
Innovation Solution
An anti-fuse memory circuit is designed with a memory array, bit lines, word lines, a second switch transistor, a reading circuit, and a signal generation circuit that adjusts the sampling signal delay based on the precharge voltage, ensuring accurate data reading by comparing the input voltage with a reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed reference voltage is used for reading anti-fuse memory cells, then the reading circuit structure is simple, but read errors occur when VDD fluctuates between high and low levels
Solution Approach 1:
The patent applies dynamics by making the reference voltage adjustable rather than fixed. The reference voltage generation circuit dynamically sets the reference voltage to match the current VDD level (high or low), allowing the reading circuit to adapt to voltage fluctuations and prevent read errors while maintaining simple circuit structure
Solution Approach 2:
The patent changes the parameter of reference voltage based on VDD fluctuations. By generating different reference voltages corresponding to high and low VDD levels, the system maintains accurate data reading across varying voltage conditions without increasing structural complexity
2Device complexity
If the sampling signal is generated with fixed delay, then the signal generation is simple, but data reading accuracy decreases when precharge voltage varies
Solution Approach 1:
The patent applies dynamics by making the sampling signal delay adjustable. The signal generation circuit dynamically adjusts the delay duration based on the precharge voltage level, ensuring optimal sampling timing for accurate data reading regardless of voltage conditions
Solution Approach 2:
The patent uses feedback by having the signal generation circuit detect the precharge voltage level and accordingly adjust the sampling signal delay. This feedback mechanism ensures that the sampling timing is optimized for the current voltage condition, maintaining high reading accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures accurate data reading by dynamically adjusting the sampling signal delay in response to precharge voltage fluctuations, preventing read errors and maintaining data integrity across varying voltage conditions.
Implementation Method 1
Gate oxygen media of the anti-fuse memory cells are broken down after a high voltage is applied, and an impedance of a path decreases after the breakdown
Implementation Method 2
the reading circuit compares an input voltage of the first input terminal with the reference voltage, to output 1-bit data stored in the anti-fuse memory cell
Data Source
AI summary
An anti-fuse memory circuit includes: a memory array including multiple anti-fuse memory cells; bit lines, each connected to the anti-fuse memory cells arranged in extension direction of the bit line, each anti-fuse memory cell being electrically connected to respective one of bit lines through first switch transistor; word lines, each connected to first switch transistors arranged in extension direction of word line; a second switch transistor connects one of the bit lines to transmission wire; a reading circuit, having first input terminal connected to the transmission wire, second input terminal for receiving reference voltage, and sampling input terminal for receiving sampling signal; and a signal generation circuit for generating sampling signal according to precharge voltage and precharge signal, where precharge signal is used for instructing to precharge transmission wire to precharge voltage, and delay duration between sampling signal and precharge signal is positively correlated with voltage amplitude of precharge voltage.