Antifuse Memory Cell Integration with Standard CMOS
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in integrating with standard CMOS integrated circuitry without requiring additional processing steps or special structures, limiting their integration with other CMOS circuitry.
Innovation Solution
A non-volatile memory cell structure utilizing an antifuse element and a capacitor, where the antifuse element is a MOS transistor with a gate, source, and drain coupled to the same voltage level, allowing for programming through voltage pulses, enabling integration with standard CMOS processing and eliminating the need for high voltage transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing non-volatile memory technologies are used, then non-volatile storage is achieved, but integration with standard CMOS circuitry requires additional processing steps or special structures
Solution Approach 1:
The patent makes the MOS transistor serve dual functions: as a standard CMOS transistor for logic circuitry and as an antifuse element for non-volatile memory. By configuring the transistor with source, drain, and well coupled to the same voltage level, it can operate in both contexts without requiring separate structures or additional processing steps, thus resolving the contradiction between ease of manufacture and device complexity
Solution Approach 2:
The patent changes the voltage level parameter of the source, drain, and well to be equal, which enables the transistor to function as an antifuse element. This parameter change allows the same structure to provide non-volatile memory functionality without additional processing, improving ease of manufacture while maintaining simple device structure
2Ease of operation
If high voltage transistors are used for programming, then programming capability is achieved, but device complexity and processing difficulty increase
Solution Approach 1:
The patent enables the memory cell to generate its own high programming voltage internally through the capacitor discharge mechanism, eliminating the need for external high voltage transistors or separate high voltage generation circuitry. The capacitor stores energy and releases it as a high voltage pulse to program the antifuse element, providing programming capability while maintaining simple device structure and reducing overall system complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the integration of non-volatile memory with other CMOS circuitry using standard CMOS processes, allowing for internal voltage doubling within the memory cell, reducing the need for special processing and high voltage transistors, and providing a scalable solution for embedded memory architectures.
Implementation Method 1
The capacitor element is coupled to the antifuse element and is configured to provide the one or more voltage pulses to the programming node
Implementation Method 2
The antifuse element is configured to have changed resistivity after the programming node is subjected to one or more voltage pulses, the change in resistivity representing a change in logic state
Data Source
AI summary
A non-volatile memory cell and associated programming methods that allow for integration of non-volatile memory with other CMOS integrated circuitry utilizing standard CMOS processing. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor element coupled to the antifuse element and configured to provide one or more voltage pulses to the programming node. The antifuse element is configured to have a changed resistivity after the programming node is subjected to the one or more voltage pulses, the change in resistivity representing a change in logic state. The antifuse element comprises a MOS transistor, its gate being coupled to one of the programming node and a control node, and its source and drain being coupled to the other one of the programming node and the control node. The MOS transistor is formed in a well and the source, drain and well are coupled to the same voltage level.