Anti-Fuse Memory Cell Layout With 2D/3D Transistors for Fast Readout
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Solution Overview
Problem
Existing memory devices face challenges in achieving compact design and fast reading speed while maintaining non-volatile data storage capabilities, particularly in anti-fuse memory cells.
Innovation Solution
The integration of anti-fuse memory cells with a combination of two-dimensional (2D) and three-dimensional (3D) transistors, along with specific transistor configurations and metallization layer arrangements, reduces the device area and enhances reading speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional memory device designs are used, then non-volatile data storage is achieved, but the device area is large and reading speed is slow
Solution Approach 1:
The patent transitions from planar 2D transistor structures to 3D vertically-channel-transistor structures, utilizing the vertical dimension to increase functional density without expanding the horizontal device footprint. This dimensional transition enables faster reading speeds while maintaining compact device area.
Solution Approach 2:
The patent implements nested transistor configurations where vertically-channel transistors are integrated within multi-layer metallization structures. The 3D transistors are positioned vertically above substrate regions, with multiple metallization layers stacked above them, creating a nested arrangement that maximizes space utilization and improves reading speed without increasing device area.
2Area of stationary object
If device area is reduced for compact design, then integration density increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent employs parameter changes in the form of multiple metallization layers with different conductivity types (n-type and p-type) arranged in specific sequences. This allows precise control of electrical characteristics and transistor behavior, enabling compact device design while maintaining manufacturability through standardized layer configurations that can be controlled within existing fabrication capabilities.
Solution Approach 2:
The patent uses composite metallization structures combining multiple layers of conductive materials with different properties (n-type and p-type metallization layers). This composite approach enables precise electrical control and compensates for manufacturing variations, allowing compact device design without excessive precision requirements.
Data Source
AI summary
A memory device includes a first transistor. The first transistor includes a gate structure, a gate dielectric disposed over the gate structure, a channel structure disposed over the gate dielectric, a source structure disposed over the channel structure, and a drain structure disposed over the channel structure. The memory device further includes a second transistor coupled to the first transistor. The memory device further includes a third transistor coupled to the first transistor. In some aspects, the first transistor is coupled between the second transistor and the third transistor in series. In some aspects, the source structure is coupled to a source or a drain of the second transistor and the drain structure is coupled to a source or a drain of the third transistor.