Anti-Fuse Memory Cell Structure to Minimize Leakage Paths
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Solution Overview
Problem
Existing anti-fuse memory devices suffer from reliability issues due to leakage paths in programming transistors, which can cause undesired stress on unselected cells, leading to reduced overall reliability.
Innovation Solution
The implementation of an anti-fuse memory device with a non-transistor anti-fuse structure, where a first electrode and a second electrode sandwich an insulator, allowing for electrical coupling by breaking down the insulator, eliminating the need for a programming transistor and reducing leakage paths, and allowing for compact formation of memory cells using existing CMOS technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a programming transistor is used in the anti-fuse memory cell, then the memory cell can be programmed by breaking down the gate dielectric, but leakage paths in the programming transistor cause undesired stress on unselected cells and reduce reliability
Solution Approach 1:
The patent removes the programming transistor from the anti-fuse memory cell structure, extracting the source of leakage current. The anti-fuse structure is directly connected to word lines and bit lines without requiring a programming transistor, thereby eliminating leakage paths that cause undesired stress on unselected cells.
Solution Approach 2:
The patent introduces a dummy gate structure as an intermediary element. The dummy gate is positioned over the active region where the anti-fuse structure is formed, and it serves as a placeholder that prevents direct connection between word lines and the anti-fuse structure during programming, thereby blocking leakage current paths while allowing the programming voltage to be applied to the anti-fuse structure through controlled contacts.
2Area of stationary object
If a programming transistor is included in each memory cell, then programming functionality is achieved, but the area required for each memory cell increases
Solution Approach 1:
The programming transistor is completely removed from the memory cell structure. The anti-fuse memory cell consists only of the anti-fuse structure (first electrode, second electrode, and insulator) directly connected to the word line and bit line, eliminating the need for additional transistor components and reducing the overall cell area.
Solution Approach 2:
The same anti-fuse structure serves multiple functions: it acts as both the programming element (where the insulator breakdown occurs) and the storage element (where the programmed state is retained). This multi-functionality eliminates the need for separate programming and storage components, reducing area requirements.
3Device complexity
If existing CMOS technologies are used to form anti-fuse memory cells with programming transistors, then fabrication compatibility is maintained, but the complexity of the device structure increases
Solution Approach 1:
The programming transistor is removed from the device structure, simplifying the overall architecture. The memory cell now consists only of the anti-fuse structure with its electrodes and insulator, reducing the number of components that need to be fabricated and assembled.
Solution Approach 2:
The patent introduces a dummy gate structure that is asymmetric in function - it appears where a real gate would be in a conventional transistor, but it serves only as a placeholder or spacer rather than an active switching element. This asymmetric design allows the structure to maintain compatibility with standard CMOS fabrication processes while simplifying the actual device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability of anti-fuse memory devices by minimizing leakage currents, reducing the area required for memory cell arrays, and maintaining compatibility with existing fabrication processes, resulting in a more efficient and reliable memory storage solution.
Implementation Method 1
breaking down an insulator laterally interposed between a first via structure and a second via structure by applying a second voltage on the second via structure
Data Source
AI summary
A memory device includes a first memory cell including a first transistor and a first anti-fuse structure electrically coupled to each other in series. The first transistor includes a first gate structure extending across an active region, a first source/drain structure disposed in a first portion of the active region, and a second source/drain structure disposed in a second portion of the active region. The first anti-fuse structure includes a first electrode electrically coupled to the first source/drain structure, a second electrode disposed over a first dummy gate structure, and a first insulator laterally interposed between the first electrode and the second electrode.